XCF16PVO48C XILINX [Xilinx, Inc], XCF16PVO48C Datasheet - Page 11

• Manufacturer Part Number: XCF16PVO48C
• Description: Platform Flash In-System Programmable Configuration PROMs
• Manufacturer: XILINX [Xilinx, Inc]

Larger design revisions can be split over several cascaded
PROMs. For example, two 32-Mbit PROMs can store up to
four separate design revisions: one 64-Mbit design revision,
two 32-Mbit design revisions, three 16-Mbit design revisions,
four 16-Mbit design revisions, and so on. When cascading
one 16-Mbit PROM and one 8-Mbit PROM, there are 24 Mbits
of available space, and therefore up to three separate design
revisions can be stored: one 24-Mbit design revision, two
8-Mbit design revisions, or three 8-Mbit design revisions.
See
revisions can be stored. The design revision partitioning is
handled automatically during file generation in iMPACT.
During the PROM file creation, each design revision is
assigned a revision number:
After programming the Platform Flash PROM with a set of
design revisions, a particular design revision can be
DS123 (v2.11.1) March 30, 2007
Product Specification
Revision 0 = '00'
Revision 1 = '01'
Revision 2 = '10'
Revision 3 = '11'
Figure 5
R
for a few basic examples of how multiple
4 Design Revisions
4 Design Revisions
(16 Mbits)
(16 Mbits)
(16 Mbits)
(16 Mbits)
(8 Mbits)
(8 Mbits)
(8 Mbits)
(8 Mbits)
PROM 0
PROM 0
PROM 1
REV 0
REV 1
REV 2
REV 3
REV 0
REV 1
REV 2
REV 3
(b) Design Revision storage examples spanning two XCF32P PROMs
(a) Design Revision storage examples for a single XCF32P PROM
Figure 5: Design Revision Storage Examples
3 Design Revisions
3 Design Revisions
(16 Mbits)
(16 Mbits)
(16 Mbits)
(32 Mbits)
(8 Mbits)
(8 Mbits)
PROM 0
PROM 0
PROM 1
REV 0
REV 1
REV 2
REV 0
REV 1
REV 2
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Platform Flash In-System Programmable Configuration PROMs
(16 Mbits)
(16 Mbits)
(32 Mbits)
(32 Mbits)
PROM 0
PROM 0
PROM 1
REV 0
REV 1
REV 0
REV 1
2 Design Revisions
2 Design Revisions
selected using the external REV_SEL[1:0] pins or using the
internal programmable design revision control bits. The
EN_EXT_SEL pin determines if the external pins or internal
bits are used to select the design revision. When
EN_EXT_SEL is Low, design revision selection is controlled
by the external Revision Select pins, REV_SEL[1:0]. When
EN_EXT_SEL is High, design revision selection is
controlled by the internal programmable Revision Select
control bits. During power up, the design revision selection
inputs (pins or control bits) are sampled internally. After
power up, the design revision selection inputs are sampled
again when any of the following events occur:
•
•
•
•
The data from the selected design revision is then
presented on the FPGA configuration interface.
On the rising edge of CE
On the falling edge of OE/RESET (when CE is Low)
On the rising edge of CF (when CE is Low)
When reconfiguration is initiated by using the JTAG
CONFIG instruction.
(24 Mbits)
(16 Mbits)
(16 Mbits)
(32 Mbits)
PROM 0
(8 Mbits)
PROM 0
PROM 1
REV 0
REV 1
REV 0
REV 1
REV 1
1 Design Revision
1 Design Revision
ds123_20_102103
(32 Mbits)
(32 Mbits)
(32 Mbits)
PROM 0
PROM 0
PROM 1
REV 0
REV 0
REV 0
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