XCF16PVO48C XILINX [Xilinx, Inc], XCF16PVO48C Datasheet - Page 25

• Manufacturer Part Number: XCF16PVO48C
• Description: Platform Flash In-System Programmable Configuration PROMs
• Manufacturer: XILINX [Xilinx, Inc]

Standby Mode
The PROM enters a low-power standby mode whenever CE
is deasserted (High). In standby mode, the address counter
is reset, CEO is driven High, and the remaining outputs are
placed in a high-impedance state regardless of the state of
the OE/RESET input. For the device to remain in the
low-power standby mode, the JTAG pins TMS, TDI, and
TDO must not be pulled Low, and TCK must be stopped
(High or Low).
When using the FPGA DONE signal to drive the PROM CE
pin High to reduce standby power after configuration, an
Table 11: Truth Table for XCFxxS PROM Control Inputs
Table 12: Truth Table for XCFxxP PROM Control Inputs
DS123 (v2.11.1) March 30, 2007
Product Specification
Notes:
1.
2.
Notes:
1.
2.
3.
4.
5.
OE/RESET
OE/RESET
X = don’t care.
TC = Terminal Count = highest address value.
X = don’t care.
TC = Terminal Count = highest address value.
For the XCFxxP with Design Revisioning enabled, EA = end address (last address in the selected design revision).
For the XCFxxP with Design Revisioning enabled, Reset = address reset to the beginning address of the selected bank. If Design
Revisioning is not enabled, then Reset = address reset to address 0.
The BUSY input is only enabled when the XCFxxP is programmed for parallel data output and decompression is not enabled.
High
High
High
Low
X
High
Low
X
Control Inputs
(1)
R
Control Inputs
High
Low
Low
Low
Low
CE
High
Low
Low
CE
High
High
CF
↑
X
X
If address < TC
If address = TC
Held reset
Held reset
BUSY
High
Low
X
X
X
(1)
(5)
If address < TC
address < EA
If address < TC
address = EA
Else
If address = TC
Unchanged
Reset
Held reset
Held reset
Internal Address
(2)
(2)
: increment
: don't change
(4)
Internal Address
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Platform Flash In-System Programmable Configuration PROMs
(4)
(4)
(3)
(3)
(2)
(2)
(2)
: increment
: don't change
and
and
: don't change
external pull-up resistor should be used. Typically a 330Ω
pull-up resistor is used, but refer to the appropriate FPGA
data sheet for the recommended DONE pin pull-up value. If
the DONE circuit is connected to an LED to indicate FPGA
configuration is complete, and is also connected to the
PROM CE pin to enable low-power standby mode, then an
external buffer should be used to drive the LED circuit to
ensure valid transitions on the PROM’s CE pin. If low-power
standby mode is not required for the PROM, then the CE pin
should be connected to ground.
Unchanged
Active and
High-Z
High-Z
High-Z
High-Z
Active
Active
DATA
High-Z
High-Z
High-Z
Active
DATA
CEO
High
High
High
High
High
High
Low
Outputs
Outputs
CEO
High
High
High
Low
CLKOUT
High-Z
High-Z
High-Z
High-Z
Active
Active
Active
Reduced
Standby
Active
Active
ICC
Reduced
Reduced
Standby
Active
Active
Active
Active
ICC
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