XCF16PVO48C XILINX [Xilinx, Inc], XCF16PVO48C Datasheet - Page 21

• Manufacturer Part Number: XCF16PVO48C
• Description: Platform Flash In-System Programmable Configuration PROMs
• Manufacturer: XILINX [Xilinx, Inc]

DS123 (v2.11.1) March 30, 2007
Product Specification
TMS
TDO
TCK
TDI
V
CCJ
V
CCO
Figure 11: Configuring Multiple Devices with Identical Patterns in Master/Slave SelectMAP Mode
V
CCINT
R
V
V
V
TDI
TMS
TCK
GND
Notes:
1 For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet or FPGA family
2 For compatible voltages, refer to the appropriate data sheet.
3 CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.
4 The BUSY pin is only available with the XCFxxP Platform Flash PROM (only certain FPGA families require the BUSY pin
5 For the XCFxxP the CF pin is a bidirectional pin. For the XCFxxP, if CF is not connected to PROG_B, then it must be tied
CCINT
CCO (2)
CCJ (2)
XCFxxP
Platform Flash
PROM
Cascaded
PROM
(PROM 1)
configuration user guide.
connection for high-frequency SelectMAP mode configuration). For FPGAs that do not have a BUSY pin or do not use
their BUSY pin during configuration, the Platform Flash PROM BUSY pin should be unconnected or grounded. For BUSY
pin requirements, refer to the appropriate FPGA data sheet or FPGA family configuration user guide.
to V CCO via a 4.7 kΩ pull-up resistor.
OE/RESET
BUSY
D[0:7]
CF
CEO
TDO
CLK
CE
(5)
(4)
V
CCJ
V
CCO
V
CCINT
V
V
V
TDI
TMS
TCK
GND
CCINT
CCO (2)
CCJ (2)
XCFxxP
Platform Flash
PROM
First
PROM
(PROM 0)
OE/RESET
BUSY
D[0:7]
CF
CEO
TDO
CLK
www.xilinx.com
CE
Platform Flash In-System Programmable Configuration PROMs
(5)
(4)
V
CCO (2)
(1)
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY
TDI
TMS
TCK
GND
Xilinx FPGA
Master SelectMAP
(4)
MODE PINS
RDWR_B
CS_B
TDO
(1)
I/O
I/O
(3)
(3)
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY
TDI
TMS
TCK
GND
Xilinx FPGA
Slave SelectMAP
(4)
MODE PINS
RDWR_B
CS_B
TDO
(1)
ds123_16_090306
I/O
I/O
(3)
(3)
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