XCF16PVO48C XILINX [Xilinx, Inc], XCF16PVO48C Datasheet - Page 23

• Manufacturer Part Number: XCF16PVO48C
• Description: Platform Flash In-System Programmable Configuration PROMs
• Manufacturer: XILINX [Xilinx, Inc]

DS123 (v2.11.1) March 30, 2007
Product Specification
TDI
TMS
TCK
TDO
Revision
Design
Control
V
Logic
CCJ
V
CCO
V
CCINT
R
Figure 13: Configuring Multiple Devices with Design Revisioning in Slave SelectMAP Mode
Notes:
1. For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet or FPGA family
2. For compatible voltages, refer to the appropriate data sheet.
3. RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.
4. The BUSY pin is only available with the XCFxxP Platform Flash PROM (only certain FPGA families require the BUSY
5. In Slave SelectMAP mode, the configuration interface can be clocked by an external oscillator, or optionally the
6 For the XCFxxP the CF pin is a bidirectional pin. For the XCFxxP, if CF is not connected to PROG_B, then it must be
XCFxxP
Platform Flash
PROM
Cascaded
PROM
(PROM 1)
V
V
V
TDI
TMS
TCK
EN_EXT_SEL
REV_SEL[1:0]
GND
CCINT
CCO (2)
CCJ (2)
configuration user guide.
pin connection for high-frequency SelectMAP mode configuration). For FPGAs that do not have a BUSY pin or do not
use their BUSY pin during configuration, the Platform Flash PROM BUSY pin should be unconnected or grounded. For
BUSY pin requirements, refer to the appropriate FPGA data sheet or FPGA family configuration user guide.
CLKOUT signal can be used to drive the FPGA's configuration clock (CCLK). If the XCFxxP PROM's CLKOUT signal is
used, then it must be tied to a 4.7 kΩ resistor pulled up to V
tied to V
External
Oscillator
EN_EXT_SEL
REV_SEL[1:0]
CF
DONE
PROG_B
CS_B[1:0]
OE/RESET
CCO
(5)
BUSY
CLK
D[0:7]
CF
via a 4.7 kΩ pull-up resistor
CEO
TDO
CE
(5)
(6)
(4)
V
CCJ
V
CCO
V
CCINT
XCFxxP
Platform Flash
PROM
First
PROM
(PROM 0)
VCCINT
V
V
TDI
TMS
TCK
EN_EXT_SEL
REV_SEL[1:0]
GND
CCO (2)
CCJ (2)
OE/RESET
BUSY
CLK
D[0:7]
CCO
CF
CEO
TDO
CE
(5)
(6)
(4)
.
www.xilinx.com
Platform Flash In-System Programmable Configuration PROMs
V
CCO (2)
(1)
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY
TDI
TMS
TCK
Xilinx FPGA
Slave SelectMAP
GND
(4)
MODE PINS
RDWR_B
CS_B
TDO
(1)
I/O
(3)
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY
TDI
TMS
TCK
Xilinx FPGA
Slave SelectMAP
GND
(4)
MODE PINS
RDWR_B
CS_B
TDO
(1)
ds123_18_012907
I/O
23
(3)