LPC2917/01 NXP [NXP Semiconductors], LPC2917/01 Datasheet - Page 28

• Manufacturer Part Number: LPC2917/01
• Description: ARM9 microcontroller with CAN and LIN
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
LPC2917_19_01_2
Preliminary data sheet
6.11.4.1 Pin description
6.12.1 Peripheral subsystem clock description
6.12.2 Watchdog timer
6.12 Peripheral subsystem
The vectored interrupt-controller inputs are active HIGH.
The event router module in the LPC2917/2919/01 is connected to the pins listed below.
The pins are combined with other functions on the port pins of the LPC2917/2919/01.
Table 14
position in the event-router registers and the default polarity.
Table 14.
The peripheral subsystem is clocked by a number of different clocks:
The purpose of the watchdog timer is to reset the ARM9 processor within a reasonable
amount of time if the processor enters an error state. The watchdog generates a system
reset if the user program fails to trigger it correctly within a predetermined amount of time.
Key features:
Symbol
EXTINT 7 - 0
CAN0 RXD
CAN1 RXD
I2C0_SCL
I2C1_SCL
LIN0 RXD
LIN1 RXD
SPI0 SDI
SPI1 SDI
SPI2 SDI
UART0 RXD
UART1 RXD
-
-
-
•
•
•
•
•
•
•
CLK_SYS_PESS
CLK_UART0/1
CLK_SPI0/1/2
CLK_TMR0/1/2/3
CLK_SAFE see
Internal chip reset if not periodically triggered
Timer counter register runs on always-on safe clock
shows the pins connected to the event router, and also the corresponding bit
Event-router pin connections
Direction
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
na
na
na
Section 6.7.2
Rev. 02 — 17 June 2009
Description
external interrupt input 7 - 0
CAN0 receive data input wake-up
CAN1 receive data input wake-up
I2C0 SCL clock input
I2C1 SCL clock input
LIN0 receive data input wake-up
LIN1 receive data input wake-up
SPI0 receive data input
SPI1 receive data input
SPI2 receive data input
UART0 receive data input
UART1 receive data input
CAN interrupt (internal)
VIC FIQ (internal)
VIC IRQ (internal)
LPC2917/01; LPC2919/01
ARM9 microcontroller with CAN and LIN
© NXP B.V. 2009. All rights reserved.
Default polarity
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
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