lpc2917 NXP Semiconductors, lpc2917 Datasheet
lpc2917
Available stocks
Related parts for lpc2917
lpc2917 Summary of contents
Page 1
... LPC2917/19 User Manual (see explicit references are made to the User Manual. 1.2 Intended audience This document is written for engineers evaluating and/or developing systems, hard- and/or software for the LPC2917/19. Some basic knowledge of ARM processors and architecture and ARM968E-S in particular is assumed (see 2. General description 2.1 Architectural overview The LPC2917/19 consists of: • ...
Page 2
... The ARM968E-S processor is described in detail in the ARM968E-S data sheet 2.3 On-chip flash memory system The LPC2917/19 includes a 512 kB or 768 kB flash memory system. This memory can be used for both code and data storage. Programming of the flash memory can be accomplished in several ways. It may be programmed in-system via a serial port; e.g. ...
Page 3
... NXP Semiconductors 2.4 On-chip static RAM In addition to the two 16 kB TCMs the LPC2917/19 includes two static RAM memories: one and one of 16 kB. Both may be used for code and/or data storage. Each internal SRAM has its own controller, so both memories can be accessed simultaneously from different AHB system bus layers ...
Page 4
... LPC2917FBD144 512 LPC2919FBD144 768 LPC2917_19_1 Preliminary data sheet ARM9 microcontroller with CAN and LIN RAM (kB) SMC 80 (incl TCMs) 32-bit 80 (incl TCMs) 32-bit Rev. 1.01 — 15 November 2007 LPC2917/19 Version SOT486-1 SOT486-1 LIN 2.0 Package 2 LQFP144 2 LQFP144 © NXP B.V. 2007. All rights reserved ...
Page 5
... NXP Semiconductors 5. Block diagram LPC2917/19 Vectored Interrupt FLASH Memory Controller (FMC) GLOBAL ACCEPTANCE Fig 1. LPC2917/19 block diagram LPC2917_19_1 Preliminary data sheet ARM9 microcontroller with CAN and LIN ITCM DTCM ARM968E Controller (VIC) s Embedded FLASH Memory 512/768 Modulation and Sampling ...
Page 6
... Pin description 6.2.1 General description The LPC2917/19 has up to four ports: two of 32 pins each, one of 28 pins and one of 16 pins. The pin to which each function is assigned is controlled by the SFSP registers in the SCU. The functions combined on each port pin are shown in the pin description tables in this section ...
Page 7
... PWM TRAP2 SPI2 SDI PWM1 MAT4 SPI2 SCK PWM1 MAT5 TIMER2 CAP1 SPI0 SCS0 TIMER2 CAP0 SPI0 SCS3 EXTINT3 - EXTINT2 - Rev. 1.01 — 15 November 2007 LPC2917/19 Function 3 EXTBUS D22 EXTBUS D23 EXTINT5 EXTINT4 - - PWM3 MAT5 PWM3 MAT4 EXTINT6 EXTINT7 PWM3 MAT3 PWM3 MAT2 ...
Page 8
... SPI2 SCS1 PWM3 MAT3 SPI2 SCS3 PWM3 MAT2 EXTINT1 PWM3 MAT1 EXTINT0 PWM3 MAT0 - PWM0 MAT2 - PWM0 MAT3 Rev. 1.01 — 15 November 2007 LPC2917/19 Function 3 EXTBUS D10 EXTBUS D11 EXTBUS CS3 EXTBUS CS2 - - EXTBUS D12 EXTBUS D13 EXTBUS CS1 EXTBUS CS0 EXTBUS A7 ...
Page 9
... PWM1 MAT5 ADC2 IN0 UART0 TXD ADC2 IN1 UART0 RXD UART1 TxD PWM0 CAP2 UART1 RxD PWM1 CAP0 Rev. 1.01 — 15 November 2007 LPC2917/19 Function 3 EXTBUS D24 EXTBUS D25 EXTBUS D26 EXTBUS D27 EXTBUS CS6 EXTBUS CS7 SPI0 SDI SPI0 SDO EXTBUS D28 ...
Page 10
... RSTN At activation of the RSTN pin the JTAGSEL pin is sensed as logic LOW. If this is the case the LPC2917/19 is assumed to be connected to debug hardware, and internal circuits re-program the source for the BASE_SYS_CLK to be the crystal oscillator instead of the Low-Power Ring Oscillator (LP_OSC). This is required because the clock rate when running at LP_OSC speed is too low for the external debugging environment ...
Page 11
... NXP Semiconductors 7.1.3 IEEE 1149.1 interface pins (JTAG boundary-scan test) The LPC2917/19 contains boundary-scan test logic according to IEEE 1149.1, also referred to in this document as Joint Test Action Group (JTAG). The boundary-scan test pins can be used to connect a debugger probe for the embedded ARM processor. Pin JTAGSEL selects between boundary-scan mode and debug mode ...
Page 12
... Timer 0, 1 (MTMR) PWM ADC_CLK ADC 1, 2 CAN Controller 0, 1 IVNSS_CLK GLOBAL ACCEPTANCE FILTER 2 Kbyte Static RAM LIN MASTER 0/1 Fig 3. LPC2917/19 block diagram, overview of clock areas LPC2917_19_1 Preliminary data sheet ARM9 microcontroller with CAN and LIN ITCM DTCM ARM968E IEEE 1149 ...
Page 13
... NXP Semiconductors 7.2.2 Base clock and branch clock relationship The next table contains an overview of all the base blocks in the LPC2917/19 and their derived branch clocks. A short description is given of the hardware parts that are clocked with the individual branch clocks. In relevant cases more detailed information can be found in the specific subsystem description ...
Page 14
... Timer 2 clock for counter part CLK_TMR3 Timer 3 clock for counter part CLK_ADC1 Control of ADC 1, capture sample result CLK_ADC2 Control of ADC 2, capture sample result CLK_TESTSHELL_IP Section 8.4 for details. Section 8.8 for details. Rev. 1.01 — 15 November 2007 LPC2917/19 Remark © NXP B.V. 2007. All rights reserved ...
Page 15
... LPC2917_19_1 Preliminary data sheet ARM9 microcontroller with CAN and LIN time, see init Rev. 1.01 — 15 November 2007 LPC2917/19 Section 12. During this © NXP B.V. 2007. All rights reserved ...
Page 16
... Section 7.1.3. Sector size (kB) Sector base address 8 0000 0000h 8 0000 2000h 8 0000 4000h Rev. 1.01 — 15 November 2007 LPC2917/19 Section 7.2.2. © NXP B.V. 2007. All rights reserved ...
Page 17
... WST ! 1 – tclk sys t acc addr --------------------- - WST ! 1 – t tclk sys Rev. 1.01 — 15 November 2007 LPC2917/19 Section 4 “Ordering information”. © NXP B.V. 2007. All rights reserved ...
Page 18
... AHB bus) if speculative reading is active. 8.2 External static memory controller 8.2.1 Overview The LPC2917/19 contains an external Static Memory Controller (SMC) which provides an interface for external (off-chip) memory devices. Key features are: • Supports static memory-mapped devices including RAM, ROM, flash, burst ROM and external I/O devices • ...
Page 19
... External static-memory controller pin description The external static-memory controller module in the LPC2917/19 has the following pins, which are combined with other functions on the port pins of the LPC2917/19. shows the external memory controller pins. Table 12. External memory controller pins Symbol ...
Page 20
... Fig 5. Writing to external memory LPC2917_19_1 Preliminary data sheet ARM9 microcontroller with CAN and LIN CLK(SYS) CS OE_N ADDR DATA WSTOEN WST1 CLK(SYS) CS WE_N / BLS ADDR DATA WSTWEN WST2 Rev. 1.01 — 15 November 2007 LPC2917/19 Figure 5. The relationship © NXP B.V. 2007. All rights reserved ...
Page 21
... I/O pin is programmed for the correct function. Control of these settings is handled by the SCU. LPC2917_19_1 Preliminary data sheet ARM9 microcontroller with CAN and LIN WSTOEN WST1 IDCY Rev. 1.01 — 15 November 2007 LPC2917/19 Figure 6. Extra wait states WSTWEN WST2 © NXP B.V. 2007. All rights reserved ...
Page 22
... The system control unit takes care of system-related functions.The key feature is configuration of the I/O port-pins multiplexer. 8.3.3.2 Description The system control unit defines the function of each I/O pin of the LPC2917/19. The I/O pin configuration should be consistent with peripheral function usage. 8.3.3.3 SCU pin description The SCU has no external pins. ...
Page 23
... The vectored interrupt-controller inputs are active HIGH. 8.3.4.3 Event-router pin description and mapping to register bit positions The event router module in the LPC2917/19 is connected to the pins listed below. The pins are combined with other functions on the port pins of the LPC2917/19. shows the pins connected to the event router, and also the corresponding bit position in the event-router registers and the default polarity ...
Page 24
... CLK_SYS_PESS. The timer and prescale counters are clocked by CLK_SAFE which is always on. 8.4.3 Timer 8.4.3.1 Overview The LPC2917/19 contains six identical timers: four in the peripheral subsystem and two in the Modulation and Sampling Control SubSystem (MSCSS) located at different peripheral base addresses. This section describes the four timers in the peripheral subsystem. Each LPC2917_19_1 ...
Page 25
... See section clocks. 8.4.3.3 Pin description The four timers in the peripheral subsystem of the LPC2917/19 have the pins described below. The two timers in the modulation and sampling subsystem have no external pins except for the pause pin on MSCSS timer 1. See timers and their associated pins. The timer pins are combined with other functions on the port pins of the LPC2917/19, see runs from ...
Page 26
... LPC2917/19 contains two industry-standard 550 UARTs with 16-byte transmit and receive FIFOs, but they can also be put into 450 mode without FIFOs. 8.4.4.3 UART pin description The two UARTs in the LPC2917/19 have the following pins. The UART pins are combined with other functions on the port pins of the LPC2917/19. runs from 0 to 1). ...
Page 27
... CLK_SYS_PESS. The baud generator is clocked by the CLK_UARTx. 8.4.5 Serial peripheral interface 8.4.5.1 Overview The LPC2917/19 contains three Serial Peripheral Interface modules (SPIs) to allow synchronous serial communication with slave or master peripherals. The key features are: • Master or slave operation • ...
Page 28
... Slave mode 8.4.5.4 SPI pin description The three SPI modules in the LPC2917/19 have the pins listed below. The pins are combined with other functions on the port pins of the LPC2917/19, see Table 16 shows the SPI pins (x runs from runs from 0 to 3). ...
Page 29
... GPIO pin description The five GPIO ports in the LPC2917/19 have the pins listed below. The GPIO pins are combined with other functions on the port pins of the LPC2917/19. GPIO pins. ...
Page 30
... It is also possible to define identifier groups for standard and extended message formats. 8.5.3 CAN pin description The two CAN controllers in the LPC2917/19 have the pins listed below. The CAN pins are combined with other functions on the port pins of the LPC2917/19. CAN pins (x runs from 0 to 1). ...
Page 31
... Fractional baud-rate generator 8.6.2 LIN pin description The two LIN 2.0 master controllers in the LPC2917/19 have the pins listed below. The LIN pins are combined with other functions on the port pins of the LPC2917/19. shows the LIN pins. For more information see controller. ...
Page 32
... TIMER 1 0 PWM PWM 1 CONTROL PWM 2 CARRIERS Figure 8 shows how the timers are connected to the ADC and Rev. 1.01 — 15 November 2007 LPC2917/19 ADC 2 3.3 V PWM0 MAT[5:0] PWM1 MAT[5:0] PWM2 MAT[5:0] PWM3 MAT[5:0] PWM 3 002aad348 © NXP B.V. 2007. All rights reserved ...
Page 33
... The signals connected to the capture inputs of the timers (both MSCSS timer 0 and MSCSS timer 1) are intended for debugging. LPC2917_19_1 Preliminary data sheet ARM9 microcontroller with CAN and LIN Figure 8, the sync_out of ADC1 is connected to the Rev. 1.01 — 15 November 2007 LPC2917/19 © NXP B.V. 2007. All rights reserved ...
Page 34
... TE_i = trans_enable_in TE_o = trans_enable_out Fig 8. Modulation and sampling-control subsystem synchronization and triggering 8.7.3 MSCSS pin description The pins of the LPC2917/19 MSCSS associated with the two ADC modules are described in Section 8.7.5.3. Pins directly connected to the four PWM modules are described in Section 8 ...
Page 35
... BASE_CLK_ADC. If specific PWM or ADC modules are not used their corresponding clocks can be switched off. 8.7.5 Analog-to-digital converter 8.7.5.1 Overview The MSCSS in the LPC2917/19 includes two 10-bit successive-approximation analog-to-digital converters. The key features of the ADC interface module are: • ADC1 and ADC2: Eight analog inputs; time-multiplexed; measurement range up to 3.3 V • ...
Page 36
... Fig 9. ADC block diagram 8.7.5.3 ADC pin description The two ADC modules in the MSCSS have the pins described below. The ADCx input pins are combined with other functions on the port pins of the LPC2917/19. The VREFN and VREFP pins are common for both ADCs. Table 20. ...
Page 37
... Control logic for the analog section of the ADC is clocked by CLK_ADCx, see also Figure 9. 8.7.6 PWM 8.7.6.1 Overview The MSCSS in the LPC2917/19 includes four PWM modules with the following features. • Six pulse-width modulated output signals • Double edge features (rising and falling edges programmed individually) • ...
Page 38
... Several PWMs can be synchronized using the trans_enable_in/trans_enable_out and sync_in/sync_out ports. See Section 8.7.2.1 in the LPC2917/19. PWM 0 can be master over PWM 1; PWM 1 can be master over PWM 2, etc. LPC2917_19_1 Preliminary data sheet ARM9 microcontroller with CAN and LIN ...
Page 39
... A PWM module can use input signals trans_enable_in and sync_in to synchronize its internal PWM counter and the transfer of shadow registers (Slave mode). 8.7.6.5 PWM pin description Each of the four PWM modules in the MSCSS has the following pins. These are combined with other functions on the port pins of the LPC2917/19. PWM3 pins. Table 21. PWM pins ...
Page 40
... If a timer module is not used its CLK_MSCSS_MTMRx branch clock can be switched off. 8.8 Power, clock and reset control subsystem 8.8.1 Overview The Power, Clock and Reset Control Subsystem (PCRSS) in the LPC2917/19 includes a Clock Generator Unit (CGU), a Reset Generator Unit (RGU) and a Power Management Unit (PMU). ...
Page 41
... RGU registers Reset Output Delay Logic Input Deglitch/ POR Sync RSTN (device pin) Reset from Watchdog counter Section 7.2.2. CLK_SYS_PCRSS is derived from Rev. 1.01 — 15 November 2007 LPC2917/19 PMU branch clocks AHB Master Disable Grant AHB Master Disable Req wakeup_a AHB_RST ... ... ...
Page 42
... BASE_SPI_CLK 7 BASE_TMR_CLK 8 BASE_ADC_CLK [1] Maximum frequency that guarantees stable operation of the LPC2917/19. [2] Fixed to low-power oscillator. For generation of these base clocks, the CGU consists of primary and secondary clock generators and one output generator for each base clock. LPC2917_19_1 Preliminary data sheet ARM9 microcontroller with CAN and LIN ...
Page 43
... ARM9 microcontroller with CAN and LIN Clock Source Bus PLL FDIV0 FDIV1 FDIV6 Frequency Clock Monitor Detection DTL MMIO Interface Figure 12. For every output generator - generating the base clocks - a Rev. 1.01 — 15 November 2007 LPC2917/19 OUT 0 OUT 1 OUT 9 © NXP B.V. 2007. All rights reserved ...
Page 44
... LPC2917_19_1 Preliminary data sheet ARM9 microcontroller with CAN and LIN OSC1M XO50M PLL160M clkout / clkout120 / clkout240 Every secondary clock generator or output generator is Rev. 1.01 — 15 November 2007 LPC2917/19 FDIV0..6 Output Control Clock outputs © NXP B.V. 2007. All rights reserved ...
Page 45
... Clocks that are inactive are automatically regarded as invalid, Provisions are included in the CGU to allow clocks to be Figure 14. The input clock is fed directly to the 2 . These clocks are either divided by 2*P by the programmable post divider Rev. 1.01 — 15 November 2007 LPC2917/19 Table 31, Dynamic characteristics. © NXP B.V. 2007. All rights reserved ...
Page 46
... PLL is not in lock. When power-down mode is terminated by clearing the PD control-register bit the PLL resumes normal operation, and makes the LOCK signal high once it has regained lock on the input clock. 8.8.4.4 CGU pin description The CGU module in the LPC2917/19 has the pins listed in Table 24. CGU pins Symbol ...
Page 47
... PWM modules WARM_RST all ADC modules WARM_RST all Timer modules in MSCSS WARM_RST Vectored Interrupt Controller (VIC) WARM_RST CPU and AHB Multilayer Bus infrastructure Rev. 1.01 — 15 November 2007 LPC2917/19 Table 25. The first five resets © NXP B.V. 2007. All rights reserved ...
Page 48
... Using the base clocks from the CGU as input, the PMU generates branch clocks to the rest of the LPC2917/19. Output clocks branched from the same base clock are phase- and frequency-related. These branch clocks can be individually controlled by software programming ...
Page 49
... BASE_SYS_CLK + BASE_SYS_CLK + BASE_SYS_CLK + BASE_PCR_CLK + BASE_IVNSS_CLK + BASE_IVNSS_CLK + BASE_IVNSS_CLK + BASE_IVNSS_CLK + BASE_IVNSS_CLK + BASE_MSCSS_CLK + BASE_MSCSS_CLK + BASE_MSCSS_CLK + BASE_MSCSS_CLK + BASE_MSCSS_CLK + BASE_MSCSS_CLK + BASE_MSCSS_CLK + + + BASE_UART_CLK + BASE_UART_CLK + Rev. 1.01 — 15 November 2007 LPC2917/19 AUTO RUN ...
Page 50
... CLK_TESTSHELL_IP 8.8.6.3 PMU pin description The PMU has no external pins. 8.9 Vectored interrupt controller 8.9.1 Overview The LPC2917/19 contains a very flexible and powerful Vectored Interrupt Controller (VIC) to interrupt the ARM processor on request. The key features are: • Level-active interrupt request with programmable polarity • ...
Page 51
... Testing RTOS interrupt handling without using device-specific interrupt service routines • Software emulation of an interrupt-requesting device, including interrupts 8.9.3 VIC pin description The VIC module in the LPC2917/19 has no external pins. 8.9.4 VIC clock description The VIC is clocked by CLK_SYS_VIC, see 9. Limiting values Table 28. ...
Page 52
... Charged device model. On corner pins. Charged device model. . I(ADC) limits the allowable combinations of power dissipation and ambient temperature. vj Parameter Conditions thermal resistance from in free air junction to ambient package; LQFP144 Rev. 1.01 — 15 November 2007 LPC2917/19 Min Max Unit - mA 33 - +38 mA 40 +150 qC +85 40 ...
Page 53
... All other I/O pins, -0.5 RESET_N, TRST_N, TDI, JTAGSEL, TMS, TCK. 2.0 TRST_N, TDI, JTAGSEL, TMS, TCK. All port pins, RESET_N, - TRST_N, TDI, JTAGSEL, TMS, TCK. 0.4 - Rev. 1.01 — 15 November 2007 LPC2917/ +125 q C; all voltages are [1] Typ Max Unit 1.80 1.89 V 1.1 2.5 mA/ MHz ...
Page 54
... V OH DD(IO VREFN Port 0. V VREFN Between VREFN and 4.4 VREFP Between VREFN and 13.7 VDD(A5V 20 20 Rev. 1.01 — 15 November 2007 LPC2917/ +125 q C; all voltages are [1] Typ Max Unit - 100 PA 50 100 DD(IO) – 0.4 ...
Page 55
... V for 2 Ps before reset is de-asserted; V trip(high) . I(ADC DD(A3V3) vj Conditions Min Rev. 1.01 — 15 November 2007 LPC2917/ +125 q C; all voltages are [1] Typ Max Unit - 160 : - ...
Page 56
... MHz; i(ADC /(n+1) with s i(ADC resolution resolution 2 bit - resolution 10 bit - In number of ADC clock 3 cycles. In number of bits 0. Rev. 1.01 — 15 November 2007 LPC2917/ all voltages are measured with Typ Max Unit - 80 MHz - 100 ns 0.4 0.42 MHz 6 100 MHz 500 - MHz ...
Page 57
... Master operation 65024 clk(spi) 1 Slave operation 65024 clk(spi) [ (final testing). Both pre-testing and final testing use correlated amb Rev. 1.01 — 15 November 2007 LPC2917/ all voltages are measured with Typ Max Unit - 24 MHz 2 clk(uart ...
Page 58
... scale (1) ( 20.1 20.1 22.15 22.15 0.75 1 0.5 19.9 19.9 21.85 21.85 0.45 REFERENCES JEDEC JEITA MS-026 Rev. 1.01 — 15 November 2007 LPC2917/19 SOT486 θ detail X (1) ( θ 1.4 1.4 7 0.2 0.08 0.08 o 1.1 1.1 0 EUROPEAN ISSUE DATE PROJECTION 00-03-14 03-02-20 © NXP B.V. 2007. All rights reserved. ...
Page 59
... The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 32 LPC2917_19_1 Preliminary data sheet ARM9 microcontroller with CAN and LIN Figure and 33 Rev. 1.01 — 15 November 2007 LPC2917/ the stg(max) 16) than a PbSn process, thus © NXP B.V. 2007. All rights reserved ...
Page 60
... Figure 16. maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature Rev. 1.01 — 15 November 2007 LPC2917/19 t 350 220 220 > 2000 260 245 245 peak temperature time 001aac844 © NXP B.V. 2007. All rights reserved. ...
Page 61
... DBS, DIP, HDIP, RDBS, SDIP, SIL [4] Through-hole-surface PMFP mount LPC2917_19_1 Preliminary data sheet ARM9 microcontroller with CAN and LIN Soldering method Wave suitable [3] suitable not suitable Rev. 1.01 — 15 November 2007 LPC2917/19 [2] Reflow Dipping suitable not suitable © NXP B.V. 2007. All rights reserved ...
Page 62
... ARM9 microcontroller with CAN and LIN Soldering method Wave [5] , LBGA, not suitable [5] , [6] not suitable suitable [7][8] not recommended [9] not recommended [10] , WQCCN..L not suitable Rev. 1.01 — 15 November 2007 LPC2917/19 …continued [2] Reflow Dipping suitable suitable suitable suitable suitable not suitable © NXP B.V. 2007. All rights reserved ...
Page 63
... SCU Function Select Port x,y (use without the P if there are no x,y) Slot Control List Buffer Entry List Current Controlled Oscillator Built-In Self Test Reduced Instruction Set Computer Universal Asynchronous Receiver Transmitter VLSI Peripheral bus Rev. 1.01 — 15 November 2007 LPC2917/19 © NXP B.V. 2007. All rights reserved ...
Page 64
... NXP Semiconductors 16. References [1] UM — LPC2917/19 user manual [2] ARM — ARM web site [3] ARM-SSP — ARM primecell synchronous serial port (PL022) technical reference manual [4] CAN — ISO 11898-1: 2002 road vehicles - Controller Area Network (CAN) - part 1: data link layer and physical signalling [5] LIN — ...
Page 65
... Part LPC2915 removed • Editorial updates LPC2915_17_19_1 20070917 LPC2917_19_1 Preliminary data sheet ARM9 microcontroller with CAN and LIN Data sheet status Change notice Preliminary data sheet Preliminary data sheet Rev. 1.01 — 15 November 2007 LPC2917/19 Supersedes LPC2915_17_19_1 © NXP B.V. 2007. All rights reserved ...
Page 66
... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 1.01 — 15 November 2007 LPC2917/19 © NXP B.V. 2007. All rights reserved ...
Page 67
... SPI pin description . . . . . . . . . . . . . . . . . . . . . 28 8.4.5.5 SPI clock description . . . . . . . . . . . . . . . . . . . 28 8.4.6 General-purpose I 8.4.6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.4.6.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.4.6.3 GPIO pin description . . . . . . . . . . . . . . . . . . . 29 8.4.6.4 GPIO clock description . . . . . . . . . . . . . . . . . 29 8.5 CAN gateway . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.5.2 Global acceptance filter . . . . . . . . . . . . . . . . . 30 8.5.3 CAN pin description . . . . . . . . . . . . . . . . . . . . 30 8.6 LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.6.2 LIN pin description . . . . . . . . . . . . . . . . . . . . . 31 Rev. 1.01 — 15 November 2007 LPC2917/19 continued >> © NXP B.V. 2007. All rights reserved ...
Page 68
... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 November 2007 Document identifier: LPC2917_19_1 All rights reserved. ...