STM32F103C4H6ATR STMICROELECTRONICS [STMicroelectronics], STM32F103C4H6ATR Datasheet - Page 52

• Manufacturer Part Number: STM32F103C4H6ATR
• Description: Low-density performance line, ARM-based 32-bit MCU with 16 or 32 KB Flash, USB, CAN, 6 timers, 2 ADCs, 6 communication interfaces
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

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I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in
performed under the conditions summarized in
compliant.
Table 34.
1. FT = Five-volt tolerant.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable
All I/Os are CMOS and TTL compliant (no software configuration required), their
characteristics consider the most strict CMOS-technology or TTL parameters:
●
●
Symbol
V
R
R
C
V
V
V
V
I
production.
PMOS/NMOS. This MOS/NMOS contribution
lkg
hys
PU
PD
IH
IH
IO
IL
IL
For V
–
–
For V
–
–
Input low level voltage
Standard IO input high level
voltage
IO FT
Input low level voltage
Input high level voltage
Standard IO Schmitt trigger
voltage hysteresis
IO FT Schmitt trigger voltage
hysteresis
Input leakage current
Weak pull-up equivalent
resistor
Weak pull-down equivalent
resistor
I/O pin capacitance
if V
if V
if V
if V
IH
IL
:
:
I/O static characteristics
DD
DD
DD
DD
(1)
is in the [2.00 V - 3.08 V] range: CMOS characteristics but TTL included
is in the [3.08 V - 3.60 V] range: TTL characteristics but CMOS included
is in the [2.00 V - 2.28 V] range: TTL characteristics but CMOS included
is in the [2.28 V - 3.60 V] range: CMOS characteristics but TTL included
(5)
(5)
input high level voltage
(2)
Parameter
(2)
(4)
Doc ID 15060 Rev 3
to the series resistance is minimum
V
Standard I/Os
CMOS ports
SS
Conditions
TTL ports
V
V
V

I/O FT
IN
IN
IN
V


= 5 V
Table
IN
V
V

DD
SS
V
DD
Table 34
9. All I/Os are CMOS and TTL
5% V
0.65 V
–0.5
–0.5
Min
200
30
30
2
2
are derived from tests
DD
DD
(3)
(~10% order)
Typ
40
40
5
0.35 V
.
V
V
DD
DD
5.5V
Max
0.8
1
50
50
3
+0.5
+0.5
DD
Unit
mV
mV
µA
k
k
pF
V
V