MCF5270 FREESCALE [Freescale Semiconductor, Inc], MCF5270 Datasheet - Page 11

• Manufacturer Part Number: MCF5270
• Description: 32-bit Embedded Controller Division
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

and UARTs. The DMA controller supports single or dual address to off-chip devices or dual address to
on-chip devices.
3.17 External Interface Module (EIM)
The external bus interface handles the transfer of information between the core and memory, peripherals,
or other processing elements in the external address space. Features have been added to support external
Flash modules, for secondary wait states on reads and writes, and a signal to support Active-Low Address
Valid (a signal on most Flash memories).
Programmable chip-select outputs provide signals to enable external memory and peripheral circuits,
providing all handshaking and timing signals for automatic wait-state insertion and data bus sizing.
Base memory address and block size are programmable, with some restrictions. For example, the starting
address must be on a boundary that is a multiple of the block size. Each chip select can be configured to
provide read and write enable signals suitable for use with most popular static RAMs and peripherals. Data
bus width (8-bit, 16-bit, or 32-bit) is programmable on all chip selects, and further decoding is available
for protection from user mode access or read-only access.
3.18 SDRAM Controller
The SDRAM controller provides all required signals for glueless interfacing to a variety of
JEDEC-compliant SDRAM devices. SD_SRAS/SD_SCAS address multiplexing is software configurable
for different page sizes. To maintain refresh capability without conflicting with concurrent accesses on the
address and data buses, SD_RAS, SD_SCAS, SD_WE, SD_CS[1:0] and SD_CKE are dedicated SDRAM
signals.
3.19 Reset
The reset controller is provided to determine the cause of reset, assert the appropriate reset signals to the
system, and keep track of what caused the last reset. The power management registers for the internal
low-voltage detect (LVD) circuit are implemented in the reset module. There are six sources of reset:
External reset on the RSTOUT pin is software-assertable independent of chip reset state. There are also
software-readable status flags indicating the cause of the last reset.
Freescale Semiconductor
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External
Power-on reset (POR)
Watchdog timer
Phase locked-loop (PLL) loss of lock
PLL loss of clock
Software
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2
Features
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