MCF5270 FREESCALE [Freescale Semiconductor, Inc], MCF5270 Datasheet - Page 37

• Manufacturer Part Number: MCF5270
• Description: 32-bit Embedded Controller Division
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

8.5
Table 30
Freescale Semiconductor
NOTES:
1
2
3
freq
B0
B1a
B1b
B2a
B2b
B4
B5
Name
Timing specifications are tested using full drive strength pad configurations in a 50ohm transmission line
environment..
TEA and TA pins are being referred to as control inputs.
Refer to figure A-19.
7
8
9
10
11
12
13
14
15
lists processor bus input timings.
External Interface Timing Characteristics
This specification applies to the period required for the PLL to relock after changing the MFD frequency
control bits in the synthesizer control register (SYNCR).
Assuming a reference is available at power up, lock time is measured from the time V
valid to RSTOUT negating. If the crystal oscillator is being used as the reference for the PLL, then the
crystal start up time must be added to the PLL lock time to determine the total start-up time.
2).
PLL is operating in 1:1 PLL mode.
Jitter is the average deviation from the programmed frequency measured over the specified interval at
maximum f
stable external clock signal. Noise injected into the PLL circuitry via V
crystal oscillator frequency increase the Cjitter percentage for a given interval.
Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of
Cjitter+Cmod.
Modulation percentage applies over an interval of 10µs, or equivalently the modulation rate is 100KHz.
Modulation rate selected must not result in f
Modulation range determined by hardware design.
f
t
sys/2
lpll
System bus frequency
CLKOUT period
Control input valid to CLKOUT high
BKPT valid to CLKOUT high
CLKOUT high to control inputs invalid
CLKOUT high to asynchronous control input BKPT invalid
Data input (D[31:0]) valid to CLKOUT high
CLKOUT high to data input (D[31:0]) invalid
= (64
= f
All processor bus timings are synchronous; that is, input setup/hold and
output delay with respect to the rising edge of a reference clock. The
reference clock is the CLKOUT output.
All other timing relationships can be derived from these values.
ico
*
/ (2
sys/2
4
*
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2
5 + 5 τ) T
*
. Measurements are made with the device powered by filtered supplies and clocked by a
2
RFD
Table 30. Processor Bus Input Timing Specifications
)
ref
, where T
3
Characteristic
ref
2
= 1/F
2
sys/2
Control Inputs
ref_crystal
Data Inputs
1
NOTE
value greater than the f
= 1/F
ref_ext
3
= 1/F
DDSYN
ref_1:1
sys/2
Preliminary Electrical Characteristics
, and τ = 1.57x10
and V
maximum specified value.
f
t
t
t
Symbol
sys/2
cyc
CVCH
CHCII
t
t
t
BKVCH
BKNCH
t
DIVCH
CHDII
SSSYN
DD
and V
and variation in
Min
50
9
9
0
0
4
0
-6
DDSYN
2(MFD +
Max
1/50
50
—
—
—
—
—
—
are
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
37