M38039G4H-XXXHP RENESAS [Renesas Technology Corp], M38039G4H-XXXHP Datasheet - Page 42

• Manufacturer Part Number: M38039G4H-XXXHP
• Description: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
• Manufacturer: RENESAS [Renesas Technology Corp]

3803 Group (Spec.H QzROM version)
Rev.1.10
REJ03B0166-0110
SERIAL INTERFACE
• Serial I/O1
Serial I/O1 can be used as either clock synchronous or
asynchronous (UART) serial I/O. A dedicated timer is also
provided for baud rate generation.
Fig 32. Block diagram of clock synchronous serial I/O1
Fig 33. Operation of clock synchronous serial I/O1
Write pulse to receive/transmit
buffer register 1 (address 0018
P4
P4
(f(X
P4
P4
Receive enable signal S
7
6
Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit
4
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
/S
5
/S
CIN
/R
/T
f(X
RDY1
CLK1
X
X
) in low-speed mode)
D
D
IN
1
1
)
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1”.
Nov 14, 2005
shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register.
continuously from the T
Serial output T
Serial input R
BRG count source selection bit
F/F
RDY1
X
X
D
D
16
1
1
)
1/4
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TBE = 0
Falling-edge detector
X
D pin.
TBE = 1
TSC = 0
Receive buffer register 1
Receive shift register 1
Serial I/O1 synchronous clock selection bit
D
D
Data bus
0
0
Transmit buffer register 1
Transmit shift register 1
Data bus
Address 0018
Shift clock
Frequency division ratio 1/(n+1)
D
D
Baud rate generator 1
1
1
Shift clock
Address 0018
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O1 mode can be selected by setting
the serial I/O1 mode selection bit of the serial I/O1 control
register (bit 6 of address 001A
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit/receive buffer register.
16
D
D
2
2
Address 001C
16
Clock control circuit
Clock control circuit
D
D
3
3
Serial I/O1 control register
Transmit interrupt source selection bit
Receive buffer full flag (RBF)
Serial I/O1 status register
16
1/4
D
D
4
4
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Receive interrupt request (RI)
Transmit buffer empty flag (TBE)
16
D
D
Transmit shift completion flag (TSC)
) to “1”.
5
5
Transmit interrupt request (TI)
Address 0019
Address 001A
D
D
6
6
Overrun error (OE)
detection
RBF = 1
TSC = 1
D
D
7
7
16
16