M38039G4H-XXXHP RENESAS [Renesas Technology Corp], M38039G4H-XXXHP Datasheet - Page 43

• Manufacturer Part Number: M38039G4H-XXXHP
• Description: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
• Manufacturer: RENESAS [Renesas Technology Corp]

3803 Group (Spec.H QzROM version)
Rev.1.10
REJ03B0166-0110
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit (b6) of the serial I/O1
control register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
Fig 34. Block diagram of UART serial I/O1
Fig 35. Operation of UART serial I/O1
(f(X
Transmit buffer
Receive buffer
receive clock
Serial output
Transmit or
CIN
write signal
Serial input
read signal
) in low-speed mode)
P4
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
P4
P4
R
T
6
4
5
X
X
/S
/R
/T
D
D
f(X
CLK1
1
1
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the setting of the transmit interrupt source
3: The receive interrupt (RI) is set when the RBF flag becomes “1”.
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0.
X
X
D
D
IN
Nov 14, 2005
selection bit (TIC) of the serial I/O1 control register.
1
1
)
TBE=0
ST detector
TSC=0
TBE=1
BRG count source selection bit
ST
ST
1/4
Page 43 of 91
Character length selection bit
D
D
7 bits
8 bits
0
Character length selection bit
0
OE
D
D
TBE=0
1
1
Serial I/O1 synchronous clock selection bit
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
PE FE
Receive buffer register 1
Receive shift register 1
ST/SP/PA generator
Frequency division ratio 1/(n+1)
Data bus
Data bus
Baud rate generator
Transmit buffer register 1
SP detector
Transmit shift register 1
Address 0018
Address 001C
The transmit and receive shift registers each have a buffer, but
the two buffers have the same address in a memory. Since the
shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer register, and receive data is
read from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
RBF=1
Address 0018
SP
SP
TBE=1
16
16
1/16
Serial I/O1 control register
ST
ST
Clock control circuit
16
D
Transmit interrupt source selection bit
D
0
0
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Serial I/O1 status register
RBF=0
D
D
1
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
1
Address 001A
1/16
Transmit buffer empty flag (TBE)
Transmit shift
completion flag (TSC)
Generated at 2nd bit in 2-stop-bit mode
UART1 control register
Transmit interrupt request (TI)
16
Address 0019
Address 001B
16
TSC=1*
SP
RBF=1
SP
16