M38039G4H-XXXHP RENESAS [Renesas Technology Corp], M38039G4H-XXXHP Datasheet - Page 53

• Manufacturer Part Number: M38039G4H-XXXHP
• Description: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
• Manufacturer: RENESAS [Renesas Technology Corp]

3803 Group (Spec.H QzROM version)
Rev.1.10
REJ03B0166-0110
Fig 44. Structure of serial I/O3 control registers
b7
b7
Nov 14, 2005
b0
b0
UART3 control register
(UART3CON : address 0033
Serial I/O3 status register
(SIO3STS : address 0031
Transmit buffer empty flag (TBE)
Receive buffer full flag (RBF)
Transmit shift completion flag (TSC)
Overrun error flag (OE)
Parity error flag (PE)
Framing error flag (FE)
Summing error flag (SE)
Not used (returns “1” when read)
Character length selection bit (CHAS)
Parity enable bit (PARE)
Parity selection bit (PARS)
Stop bit length selection bit (STPS)
P3
Not used (return “1” when read)
0: Buffer full
1: Buffer empty
0: Buffer empty
1: Buffer full
0: Transmit shift in progress
1: Transmit shift completed
0: No error
1: Overrun error
0: No error
1: Parity error
0: No error
1: Framing error
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
0: 8 bits
1: 7 bits
0: Parity checking disabled
1: Parity checking enabled
0: Even parity
1: Odd parity
0: 1 stop bit
1: 2 stop bits
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
5
/T
X
D
3
P-channel output disable bit (POFF)
Page 53 of 91
16
)
16
)
b7
b0
Serial I/O3 control register
(SIO3CON : address 0032
BRG count source selection bit (CSS)
Serial I/O3 synchronous clock selection bit (SCS)
S
Transmit interrupt source selection bit (TIC)
Transmit enable bit (TE)
Receive enable bit (RE)
Serial I/O3 mode selection bit (SIOM)
Serial I/O3 enable bit (SIOE)
0: f(X
1: f(X
0: BRG output divided by 4 when clock synchronous
1: External clock input when clock synchronous serial
0: P3
1: P3
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
0: Transmit disabled
1: Transmit enabled
0: Receive disabled
1: Receive enabled
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
0: Serial I/O3 disabled
1: Serial I/O3 enabled
RDY3
serial I/O3 is selected, BRG output divided by 16
when UART is selected.
I/O3 is selected, external clock input divided by 16
when UART is selected.
(pins P3
(pins P3
7
7
IN
IN
output enable bit (SRDY)
pin operates as normal I/O pin
pin operates as S
) (f(X
)/4 (f(X
4
4
CIN
to P3
to P3
CIN
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
) in low-speed mode)
)/4 in low-speed mode)
7
7
operate as normal I/O pins)
operate as serial I/O3 pins)
16
RDY3
)
output pin