M38039G4H-XXXHP RENESAS [Renesas Technology Corp], M38039G4H-XXXHP Datasheet - Page 46

• Manufacturer Part Number: M38039G4H-XXXHP
• Description: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
• Manufacturer: RENESAS [Renesas Technology Corp]

3803 Group (Spec.H QzROM version)
Rev.1.10
REJ03B0166-0110
<Notes concerning serial I/O1>
1. Notes when selecting clock synchronous serial I/O
1.1 Stop of transmission operation
• Note
• Reason
1.2 Stop of receive operation
• Note
1.3 Stop of transmit/receive operation
• Note
• Reason
Clear the serial I/O1 enable bit and the transmit enable bit to
“0” (serial I/O and transmit disabled).
Since transmission is not stopped and the transmission circuit
is not initialized even if only the serial I/O1 enable bit is
cleared to “0” (serial I/O disabled), the internal transmission is
running (in this case, since pins T
S
output). When data is written to the transmit buffer register in
this state, data starts to be shifted to the transmit shift register.
When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the T
operation failure occurs.
Clear the receive enable bit to “0” (receive disabled), or clear
the serial I/O1 enable bit to “0” (serial I/O disabled).
Clear both the transmit enable bit and receive enable bit to “0”
(transmit and receive disabled).
(when data is transmitted and received in the clock
synchronous serial I/O mode, any one of data transmission and
reception cannot be stopped.)
In the clock synchronous serial I/O mode, the same clock is
used for transmission and reception. If any one of transmission
and reception is disabled, a bit error occurs because
transmission and reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also
operates for data reception. Accordingly, the transmission
circuit does not stop by clearing only the transmit enable bit to
“0” (transmit disabled). Also, the transmission circuit is not
initialized by clearing the serial I/O1 enable bit to “0” (serial
I/O disabled) (refer to 1.1).
RDY1
function as I/O ports, the transmission data is not
Nov 14, 2005
Page 46 of 91
X
D
1
, R
X
D1, S
X
D
1
CLK1
pin and an
, and
2. Notes when selecting clock asynchronous serial I/O
2.1 Stop of transmission operation
• Note
• Reason
2.2 Stop of receive operation
• Note
2.3 Stop of transmit/receive operation
• Note 1 (only transmission operation is stopped)
• Reason
• Note 2 (only receive operation is stopped)
Clear the transmit enable bit to “0” (transmit disabled). The
transmission operation does not stop by clearing the serial
I/O1 enable bit to “0”.
Since transmission is not stopped and the transmission circuit
is not initialized even if only the serial I/O1 enable bit is
cleared to “0” (serial I/O disabled), the internal transmission is
running (in this case, since pins T
S
output). When data is written to the transmit buffer register in
this state, data starts to be shifted to the transmit shift register.
When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the T
operation failure occurs.
Clear the receive enable bit to “0” (receive disabled).
Clear the transmit enable bit to “0” (transmit disabled). The
transmission operation does not stop by clearing the serial
I/O1 enable bit to “0”.
Since transmission is not stopped and the transmission circuit
is not initialized even if only the serial I/O1 enable bit is
cleared to “0” (serial I/O disabled), the internal transmission is
running (in this case, since pins T
S
output). When data is written to the transmit buffer register in
this state, data starts to be shifted to the transmit shift register.
When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the T
operation failure occurs.
Clear the receive enable bit to “0” (receive disabled).
RDY1
RDY1
function as I/O ports, the transmission data is not
function as I/O ports, the transmission data is not
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
X
X
D
D
1
1
, R
, R
X
X
D
D
X
X
1
1
D
D
, S
, S
1
1
CLK1
CLK1
pin and an
pin and an
, and
, and