M38039G4H-XXXHP RENESAS [Renesas Technology Corp], M38039G4H-XXXHP Datasheet - Page 68

• Manufacturer Part Number: M38039G4H-XXXHP
• Description: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
• Manufacturer: RENESAS [Renesas Technology Corp]

3803 Group (Spec.H QzROM version)
Rev.1.10
REJ03B0166-0110
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”.
After a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
Interrupts
The contents of the interrupt request bits do not change
immediately after they have been written. After writing to an
interrupt request register, execute at least one instruction before
performing a BBC or BBS instruction.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
• In decimal mode, the values of the negative (N), overflow (V),
Timers
If a value n (between 0 and 255) is written to a timer latch, the
frequency division ratio is 1/(n+1).
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not
• The execution of these instructions does not change the
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is
• The instruction with the addressing mode which uses the value
• The bit-test instruction (BBC or BBS, etc.) to a direction
• The read-modify-write instructions (ROR, CLB, or SEB, etc.)
Use instructions such as LDM and STA, etc., to set the port
direction registers.
Serial Interface
In clock synchronous serial I/O, if the receive side is using an
external clock and it is to output the S
enable bit, the receive enable bit, and the S
to “1”.
Serial I/O1 continues to output the final bit from the T
after transmission is completed. S
high impedance after transfer is completed.
When in serial I/Os 1 and 3 (clock-synchronous mode) or in
serial I/O2, an external clock is used as synchronous clock, write
transmission data to the transmit buffer register or serial I/O2
register, during transfer clock is “H”.
to “1”, then execute an ADC or SBC instruction. After
executing an ADC or SBC instruction, execute at least one
instruction before executing a SEC, CLC, or CLD instruction.
and zero (Z) flags are invalid.
affect the MUL and DIV instruction.
contents of the processor status register.
“1”
of a direction register as an index
register
to a direction register.
Nov 14, 2005
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Page 68 of 91
RDY
pin for serial I/O2 goes to
signal, set the transmit
RDY
output enable bit
X
D pin
A/D Converter
The comparator uses capacitive coupling amplifier whose charge
will be lost if the clock frequency is too low.
Therefore, make sure that f(X
is at least on 500 kHz during an A/D conversion.
Do not execute the STP instruction during an A/D conversion.
D/A Converter
The accuracy of the D/A converter becomes rapidly poor under
the V
V is recommended. When a D/A converter is not used, set all
values of DAi conversion registers (i=1, 2) to “00
Instruction Execution Time
The instruction execution time is obtained by multiplying the
period of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The period of the internal clock φ is double of the X
high-speed mode.
Reserved Area, Reserved Bit
Do not write any data to the reserved area in the SFR area and the
special page. (Do not change the contents after reset.)
CPU Mode Register
Be sure to fix bit 3 of the CPU mode register (address 003B
“1”.
CC
= 4.0 V or less condition; a supply voltage of V
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
IN
) in the middle/high-speed mode
16
”.
IN
period in
CC
16
≥ 4.0
) to