XR16C2850CM48 EXAR [Exar Corporation], XR16C2850CM48 Datasheet - Page 19
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XR16C2850CM48
Manufacturer Part Number
XR16C2850CM48
Description
3.3V AND 5V DUART WITH 128-BYTE FIFO
Manufacturer
EXAR [Exar Corporation]
Datasheet
1.XR16C2850CM48.pdf
(43 pages)
XR16C2850
REV. 2.0.0
.
A
A2-A0
DDRESS
1 1 1
1 1 1
0 0 0
0 0 0
0 0 1
0 1 0
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
0 0 0
0 0 1
T
ABLE
EMSR
DREV
N
RHR
MCR
MSR
FLVL
DVID
THR
FCR
SPR
DLM
LCR
LSR
R
DLL
IER
ISR
AME
EG
8: INTERNAL REGISTERS DESCRIPTION.
RD/WR
RD/WR Divisor
RD/WR
RD/WR
RD/WR
RD/WR
R
W
WR
WR
WR
RD
RD
RD
RD
RD
RD
RD
EAD
RITE
/
CTS# Int.
Prescaler
RX FIFO
RX FIFO
Enabled
Enable
Trigger
Enable
Global
FIFOs
B
Error
Input
Rsvd
BRG
Bit-7
Bit-7
CD#
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
IT
0/
0/
0
3.3V AND 5V DUART WITH 128-BYTE FIFO
-7
RI# Input DSR#
RTS# Int.
RX FIFO
IR Mode
Enabled
ENable
Enable
Trigger
Set TX
THR &
FIFOs
Empty
Break
B
Rsvd
Bit-6
Bit-6
TSR
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
IT
0/
0/
0
16C550 Compatible Registers
-6
Baud Rate Generator Divisor
TX FIFO
Xoff Int..
XonAny
Enable
Source
Trigger
Empty
Parity
B
Input
Hyst.
Bit-5
Bit-5
Bit-5
THR
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Auto
RTS
bit-3
INT
Set
IT
0/
0/
0/
0/
0
-5
19
RX Break RX Fram-
TX FIFO
Lopback
Internal
Source
Enable
Trigger
Enable
Sleep
Mode
Parity
CTS#
B
Even
Input
Hyst.
Bit-4
Bit-4
Bit-4
Bit-4
Auto
RTS
Bit-4
Bit-4
Bit-4
Bit-4
INT
bit-2
IT
0/
0/
0/
1
-4
S
HADED BITS ARE ENABLED WHEN
Delta CD# Delta
Status Int.
OP2#/INT
ing Error
Modem
Source
Enable
Enable
Enable
Enable
Output
Mode
Parity
B
DMA
Rsvd
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
INT
IT
0
-3
RX Line
(OP1#)
Status-
Enable
Source
Reset
Parity
B
FIFO
Rsvd
Error
Rsvd
Bit-2
Bit-2
Bit-2
Stop
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bits
INT
RI#
Int.
RX
TX
IT
0
-2
Source
Control
Enable
Length
Output
Empty
DSR#
Count
Reset
RTS#
Rx/Tx
Over-
B
FIFO
Word
Delta
FIFO
Error
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
INT
run
Int.
RX
RX
TX
IT
1
-1
RX Data
RX Data
Source
Control
EFR B
Enable
Enable
Length
Output
Ready
FIFOs
DTR#
Rx/Tx
Count
CTS#
Word
B
Delta
FIFO
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
INT
Int.
IT
0
-0
IT
-4=1
LCR
LCR 0xBF
FCTR[6]=0
FCTR[6]=1
DLM=0x00
LCR[7] = 0
LCR[7] = 0
LCR[7] = 0
LCR[7] = 0
LCR[7] = 1
LCR[7] = 1
DLL=0x00
C
OMMENT
0xBF