M52D32162A-10TG ESMT [Elite Semiconductor Memory Technology Inc.], M52D32162A-10TG Datasheet
M52D32162A-10TG
Related parts for M52D32162A-10TG
M52D32162A-10TG Summary of contents
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... Elite Semiconductor Memory Technology Inc 16Bit x 2Banks Mobile Synchronous DRAM GENERAL DESCRIPTION The M52D32162A is 33,554,432 bits synchronous high data rate Dynamic RAM organized 1,048,576 words by 16 bits, fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle ...
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... Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device. M52D32162A LWE LDQM ...
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... IL I -10 OL ≤ 3ns acceptable. ≤ 3ns acceptable all other pins are not under test = 0V. DDQ ≤ OUT DDQ ° 1MHz) Symbol C CLK ADD C OUT M52D32162A Value -1.0 ~ 2.6 -1.0 ~ 2.6 - 150 0.7 50 ° C ° Typ Max Unit 1.8 1.9 V 1.8 V +0.3 V DDQ 0 0 ...
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... All other pins V -0. 0mA, Page Burst OL All Band Activated (min) CCD CCD ≥ (min) RFC RFC TCSR range ≤ CKE 0.2V ≤ CKE 0.2V M52D32162A ° Version -7 - 0.3 ∞ = 0.2 =15ns 3 ∞ 1.5 ∞ =15ns 10 =15ns 2 ...
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... RC t (min) 65 RFC t (min) CDL t (min) RDL t (min) BDL t (min) CCD t (max) REF CAS latency=3 CAS latency=2 after self refresh exit. RFC M52D32162A ~ 70 C ° ) Unit / 0.2 DDQ ns DDQ Vtt =0.5x VDDQ 50 Z0= (Fig.2) AC Output Load Circuit Version Unit - ...
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... Symbol Min Max 7 t 1000 SAC - SLZ - 6 t SHZ - 9 *All AC parameters are measured from half to half. M52D32162A -10 Unit Note Min Max 9 1000 ...
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... Reserved Reserved Reserved Reserved Reserved Reserved M52D32162A Burst Length Burst Length Type Sequential Interleave Reserved Reserved ...
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... ATCSR 0 0 Elite Semiconductor Memory Technology Inc TCSR PASR TCSR DS ATCSR M52D32162A A0 Address bus Extended Mode Register A2-0 Self Refresh Coverage 000 Full Array 001 1/2 of Full Array 010 1/4 of Full Array PASR 011 Reserved 100 Reserved 101 Reserved 110 ...
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... M52D32162A Interleave Addressing Sequence (decimal Interleave Addressing Sequence (decimal ...
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... Entry Exit Entry Exit (V= Valid, X= Don’t Care, H= Logic High Logic Low) after the end of burst. RP M52D32162A RAS CAS DQM BA A10/ ...
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... *Note M52D32162A *Note2,3 *Note4 *Note2 *Note 3 *Note4 ...
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... Enable auto precharge, precharge bank A at end of burst Enable auto precharge, precharge bank B at end of burst. 4. A10/AP and BA control bank precharge when precharge command is asserted. A10/AP BA precharge 0 0 Bank Bank Both Banks Elite Semiconductor Memory Technology Inc. Operation M52D32162A Publication Date : Jul. 2009 Revision : 1.6 12/32 ...
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... Elite Semiconductor Memory Technology Inc M52D32162A ...
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... Qa0 Qa1 Qa2 Qa3 Qa0 Qa1 Qa2 Qa3 Precharge Row Active (A-Bank) ) after the clock. SHZ +CAS latency-1)+t RCD M52D32162A Cb0 Rb Db1 Db2 Db0 *Note4 Db0 Db1 Db2 *Note4 (A- (A-Ban k) SAC Publication Date : Jul ...
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... HIGH Cb0 Qa0 Qb0 Qb1 Qb2 Qa1 Qa1 Qb0 Qb1 Qa0 *Note1 Read (A-Bank) before Row precharge, will be written. RDL M52D32162A *Note2 Cc0 Cd0 t RDL Dc0 Dc1 Dd1 Dd0 Dc0 Dc1 Dd0 Dd2 t CDL *Note3 ...
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... HIGH RBb CBb RBb QAa0 QAa1 QAa2 QAa3 QBb0 QAa0 QAa1 QAa3 QAa2 Read (B-Bank) Row Active (B-Bank) M52D32162A CAc CBd CAe QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QBb1 QBb0 QBb2 QBb3 QAc0 QAc1 QBd0 ...
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... Elite Semiconductor Memory Technology Inc HIGH CBb RBb RBb DBb2 DBb3 DAa1 DAa2 DAa3 DBb0 DBb1 t CDL Write (B-Bank) (B-Bank) M52D32162A *Note2 CAc CBd DAc0 DAc1 DBd0 DBd1 t RDL *Note1 Precharge Write (Both Banks) (A-Bank) Write (B-Bank) Publication Date : Jul ...
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... HIGH RBb RBb QAa2 QAa3 QAa0 QAa1 QAa1 QAa2 QAa3 QAa0 Precharge (A-Bank) Row Active (B-Bank) M52D32162A CBb RAc CAc RAc *Note1 t CDL DBb1 DBb2 DBb3 DBb0 DBb2 DBb3 DBb0 DBb1 ...
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... Read with Auto Precharge Auto Precharge Start Point ( A - Bank ) ( A - Bank) before internal precharge start RAS M52D32162A ...
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... Elite Semiconductor Memory Technology Inc M52D32162A ...
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... *Note2 M52D32162A ...
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... Elite Semiconductor Memory Technology Inc M52D32162A Publication Date : Jul ...
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... Row Active (B-Bank) Read with Auto Precharge (A-Bank) M52D32162A * ...
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... Row Active Precharge Active Power-Down Power-down Exit Entry M52D32162A Read Active Power-down Exit Publication Date : Jul. 2009 Revision : 1 ...
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... Deep Power Down. 6) Upon exiting deep power down an all bank precharge command must be issued followed by two auto refresh commands and a load mode register sequence. Elite Semiconductor Memory Technology Inc. M52D32162A Publication Date : Jul. 2009 Revision : 1.6 25/32 ...
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... Elite Semiconductor Memory Technology Inc *Note3 RAS M52D32162A required before exit from self refresh ...
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... CS , RAS , CAS & WE activation at the same clock cycle with address key will set internal mode register. 2.Minimum 2 clock cycles should be met before new RAS activation. 3.Please refer to Mode Register Set table. Elite Semiconductor Memory Technology Inc. Auto Refresh Cycle M52D32162A Publication Date : Jul ...
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... CS , RAS , CAS & WE activation at the same clock cycle with address key will set internal extended mode register. 2.Minimum 2 clock cycles should be met before new RAS activation. 3.Please refer to Mode Register Set table. Elite Semiconductor Memory Technology Inc M52D32162A Publication Date : Jul. 2009 Revision : 1.6 28/32 ...
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... D 22.22 BSC E 11.76 BSC 10.16 BSC L 0.40 0.50 0.60 0.016 0.020 0.024 L1 0.80 REF e 0.80 BSC 0° 10° Θ M52D32162A SEE DETAIL 0.21 REF 0.665 REF A 1 -C- - Dimension in inch Min Norm Max 0.047 0.018 0.008 0.875 BSC 0.463 BSC ...
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... Controlling dimension : Millimeter. Elite Semiconductor Memory Technology Inc. Dimension in mm Dimension in inch Min Norm Max Min 1.00 0.20 0.25 0.30 0.008 0.61 0.66 0.71 0.024 0.30 0.35 0.40 0.012 7.90 8.00 8.10 0.311 7.90 8.00 8.10 0.311 6.40 6.40 0.80 M52D32162A Norm Max 0.039 0.010 0.012 0.026 0.028 0.014 0.016 0.315 0.319 0.315 0.319 0.252 0.252 0.031 Publication Date : Jul. 2009 Revision : 1.6 30/32 ...
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... A9 bit of MRS 1. Add the specification Correct the voltage of absolute maximum ratings 2009.07.15 3. Correct Power Up Sequence for EMRS and add the chart of EMRS 4. Add the chart of Deep Power Down Mode M52D32162A Description ; t ; ICC1; ICC2PS; ICC6 spec SAC (1ns => 1.5ns) SH ...
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... If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Important Notice M52D32162A Publication Date : May. 2007 Revision : 1.4 32/32 ...