HD6433935 Hitachi, HD6433935 Datasheet - Page 123

• Manufacturer Part Number: HD6433935
• Description: 8-Bit MICROCONTROLLER
• Manufacturer: Hitachi

5.6
5.6.1
Subactive mode is entered from watch mode if a timer A, timer F, timer G, IRQ
WKP0 interrupt is requested while the LSON bit in SYSCR1 is set to 1. From subsleep mode,
subactive mode is entered if a timer A, timer C, timer F, timer G, SCI1, SCI31, SCI32, IRQ
IRQ
if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register.
5.6.2
Subactive mode is cleared by a SLEEP instruction or by a low input at the RES pin.
If a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and TMA3 bit in
TMA is set to 1, subactive mode is cleared and watch mode is entered. If a SLEEP instruction is
executed while SSBY = 0 and LSON = 1 in SYSCR1 and TMA3 = 1 in TMA, subsleep mode is
entered. Direct transfer to active mode is also possible; see 5.8, Direct Transfer, below.
Clearing by RES pin is the same as for standby mode; see 2. Clearing by RES pin in 5.3.2,
Clearing Standby Mode.
5.6.3
The operating frequency in subactive mode is set in bits SA1 and SA0 in SYSCR2. The choices
are ø
Clearing by SLEEP instruction
Clearing by RES pin
0
, or WKP
W
/2, ø
Subactive Mode
Transition to Subactive Mode
Clearing Subactive Mode
Operating Frequency in Subactive Mode
W
/4, and ø
7
to WKP
W
/8.
0
interrupt is requested. A transition to subactive mode does not take place
0
, or WKP
7
to
4
to
111