HD6433935 Hitachi, HD6433935 Datasheet - Page 445

• Manufacturer Part Number: HD6433935
• Description: 8-Bit MICROCONTROLLER
• Manufacturer: Hitachi

SSR31—Serial status register31
Bit
Initial value
Read/Write
Note: * Only a write of 0 for flag clearing is possible.
Transmit data register empty
0
1
Receive data register full
0
1
Overrun error
Transmit data written in TDR31 has not been transferred to TSR31
[Clearing conditions] • After reading TDRE31 = 1, cleared by writing 0 to TDRE31
Transmit data has not been written to TDR31, or transmit data written in TDR31 has been transferred to TSR31
[Setting conditions]
0
1
There is no receive data in RDR31
[Clearing conditions] • After reading RDRF31 = 1, cleared by writing 0 to RDRF31
There is receive data in RDR31
[Setting conditions] When reception ends normally and receive data is transferred from RSR31 to RDR31
Framing error
0
1
Reception in progress or completed
[Clearing conditions] After reading OER31 = 1, cleared by writing 0 to OER31
An overrun error has occurred during reception
[Setting conditions] When the next serial reception is completed with RDRF31 set to 1
Parity error
0
1
Reception in progress or completed normally
[Clearing conditions] After reading FER31 = 1, cleared by writing 0 to FER31
A framing error has occurred during reception
[Setting conditions] When the stop bit at the end of the receive data is checked for a value of 1 at completion of
Transmit end
0
1
TDRE31
Multiprocessor bit receive
Reception in progress or completed normally
[Clearing conditions] After reading PER31 = 1, cleared by writing 0 to PER31
A parity error has occurred during reception
[Setting conditions]
R/(W)
0
1
Transmission in progress
[Clearing conditions]
Transmission ended
[Setting conditions]
Multiprocessor bit transfer
7
1
0
1
• When data is written to TDR31 by an instruction
• When bit TE in serial control register 31 (SCR31) is cleared to 0
• When data is transferred from TDR31 to TSR31
Data in which the multiprocessor bit is 0 has been received
Data in which the multiprocessor bit is 1 has been received
*
• When RDR31 data is read by an instruction
A 0 multiprocessor bit is transmitted
A 1 multiprocessor bit is transmitted
RDRF31
R/(W)
reception, and the stop bit is 0
6
0
When the number of 1 bits in the receive data plus parity bit does not match the parity
designated by the parity mode bit (PM31) in the serial mode register (SMR31)
*
• After reading TDRE31 = 1, cleared by writing 0 to TDRE
• When data is written to TDR31 by an instruction
• When bit TE in serial control register 31 (SCR31) is cleared to 0
• When bit TDRE31 is set to 1 when the last bit of a transmit character is sent
OER31
R/(W)
5
0
*
FER31
R/(W)
4
0
*
PER31
R/(W)
3
0
*
TEND31
H'9C
R
2
1
MPBR31
R
1
0
MPBT31
R/W
0
0
SCI3
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