HD6433935 Hitachi, HD6433935 Datasheet - Page 80
HD6433935
Manufacturer Part Number
HD6433935
Description
8-Bit MICROCONTROLLER
Manufacturer
Hitachi
Datasheet
1.HD6433935.pdf
(521 pages)
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4. Interrupt request register 1 (IRR1)
IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer A,
SCI1, or IRQ
interrupt is accepted. It is necessary to write 0 to clear each flag.
Bit 7: Timer A interrupt request flag (IRRTA)
Bit 7
IRRTA
0
1
Bit 6: SCI1 interrupt request flag (IRRS1)
Bit 6
IRRS1
0
1
Note: SCI1 is an internal function that performs interfacing to the FLEX™ decoder incorporated in
Bit 5: Reserved bit
Bit 5 is reserved; it is always read as 1 and cannot be modified.
68
Bit
Initial value
Read/Write
Note: * Only a write of 0 for flag clearing is possible
the chip.
4
Description
Clearing conditions:
When IRRTA = 1, it is cleared by writing 0
Setting conditions:
When the timer A counter value overflows from H'FF to H'00
Description
Clearing conditions:
When IRRS1 = 1, it is cleared by writing 0
Setting conditions:
When SCI1 completes transfer
to IRQ
R/(W) *
IRRTA
7
0
0
interrupt is requested. The flags are not cleared automatically when an
R/(W) *
IRRS1
6
0
—
—
5
1
R/(W) *
IRRI4
4
0
R/(W) *
IRRI3
3
0
R/(W) *
IRRI2
2
0
R/(W) *
IRRI1
1
0
(initial value)
(initial value)
R/(W) *
IRRI0
0
0
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