P89V51RD2 Philips Semiconductors, P89V51RD2 Datasheet - Page 15

• Manufacturer Part Number: P89V51RD2
• Description: 8-bit 80C51 5 V low power 64 kB Flash microcontroller with 1 kB RAM
• Manufacturer: Philips Semiconductors

Philips Semiconductors
9397 750 12964
Product data
Table 6:
When instructions access addresses in the upper 128 bytes (above 7FH), the MCU
determines whether to access the SFRs or RAM by the type of instruction given. If it
is indirect, then RAM is accessed. If it is direct, then an SFR is accessed. See the
examples below.
Indirect Access:
Register R0 points to 90H which is located in the upper address range. Data in
‘#data’ is written to RAM location 90H rather than port 1.
Direct Access:
Data in ‘#data’ is written to port 1. Instructions that write directly to the address write
to the SFRs.
To access the expanded RAM, the EXTRAM bit must be cleared and MOVX
instructions must be used. The extra 768 bytes of memory is physically located on the
chip and logically occupies the first 768 bytes of external memory (addresses 000H to
2FFH).
When EXTRAM = 0, the expanded RAM is indirectly addressed using the MOVX
instruction in combination with any of the registers R0, R1 of the selected bank or
DPTR. Accessing the expanded RAM does not affect ports P0, P3.6 (WR), P3.7
(RD), or P2. With EXTRAM = 0, the expanded RAM can be accessed as in the
following example.
Expanded RAM Access (Indirect Addressing only):
DPTR points to 0A0H and data in ‘A’ is written to address 0A0H of the expanded
RAM rather than external memory. Access to external memory higher than 2FFH
using the MOVX instruction will access external memory (0300H to FFFFH) and will
perform in the same way as the standard 8051, with P0 and P2 as data/address bus,
and P3.6 and P3.7 as write and read timing signals.
Bit
7 to 2
1
0
MOV@R0, #data; R0 contains 90H
MOV90H, #data; write data to P1
MOVX@DPTR, A DPTR contains 0A0H
AUXR - Auxiliary register (address 8EH) bit description
Symbol
-
EXTRAM
AO
Rev. 01 — 01 March 2004
Description
Reserved for future use. Should be set to ‘0’ by user programs.
Internal/External RAM access using MOVX @Ri/@DPTR.
When ‘0’, core attempts to access internal XRAM with address
specified in MOVX instruction. If address supplied with this
instruction exceeds on-chip available XRAM, off-chip XRAM is
going to be selected and accessed.
When ‘1’, every MOVX @Ri/@DPTR instruction targets external
data memory by default.
ALE off: disables/enables ALE. AO = 0 results in ALE emitted at a
constant rate of
is active only during a MOVX or MOVC.
1
2
the oscillator frequency. In case of AO = 1, ALE
8-bit microcontrollers with 80C51 core
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
P89V51RD2
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