ST92T163 ST Microelectronics, ST92T163 Datasheet - Page 140

• Manufacturer Part Number: ST92T163
• Description: 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS
• Manufacturer: ST Microelectronics

ST92163 - USB PERIPHERAL (USB)
USB INTERFACE (Cont’d)
Bit 4 = ESUSP: End Suspend mode .
0: No activity detected during Suspend mode
1: USB activity is detected that wakes up the USB
Note: This event asynchronously clears the
LP_SUSP bit in the USBCTLR register and acti-
vates the WKUP15 internal wake-up line to notify
the
DEVCONF1 register)
Bit 3 = SUSP Suspend mode request .
0: No Suspend mode request
1: No USB traffic has been received for 3 ms.
Note: The suspend condition check is enabled im-
mediately after any USB reset and is disabled by
hardware
(LP_SUSP = 1) until the end of resume sequence.
Bit 2 = RESET: USB Reset request .
0: No USB Reset received.
1: USB Reset received.
Note: Device address and endpoint registers are
reset by an USB reset.
Bit 1 = SOF: Start Of Frame .
0: No SOF packet received.
1: SOF packet received.
Bit 0 = ESOF: Expected Start Of Frame .
0: No SOF packet missed
1: SOF packet is expected but not received.
INTERRUPT MASK REGISTER (USBIMR)
R250 - Read/Write
Register page: 15
Reset Value: 0000 0000 (00h)
This register contains mask bits for all interrupt
condition bits included in the USBISTR register.
140/224
7
0
interface during suspend mode.
DOVR
M
WUIMU
ERR
M
when
ESUSP
(if
M
suspend
STOP_CK_EN=1
SUSP
M
RESET
mode
M
SOF
is
M
in
active
ESOF
M
0
the
Whenever one of the USBIMR bits is 1, if the cor-
responding USBISTR bit is 1, an interrupt request
is generated. For an explanation of each bit, refer
to the USBISTR register description.
INTERRUPT PRIORITY REGISTER (USBIPR)
R251- Read/Write
Register page: 15
Reset Value: 0xxx 0xxx (xxh)
Bit 7 = IEE: Isochronous Endpoint Enable .
Set by software to enable Isochronous Endpoints.
This also enables CTR interrupts related to iso-
chronous endpoints and DMA overrun interrupts.
0: Isochronous endpoints disabled
1: Isochronous endpoints enabled
Bits 6:4 = PIECE[2:0]: Priority level on Iso-
chronous Endpoint and DMA Over/Underrun .
Set by software to define the priority level of the is-
ochronous endpoint CTR events (0 is the highest
priority).
Bit 3 = NIEE: Non-Isochronous Endpoint Enable .
Set by software to enable Non-Isochronous End-
points. This also enables CTR interrupts related to
non-isochronous (bulk, control, interrupt) end-
points.
0: Non-Isochronous endpoints disabled
1: Non-Isochronous endpoints enabled
Bits 2:0 = PNIEN[2:0]: Priority level of Non Iso-
chronous Endpoints and Notification.
Set by software to define the priority level of non-
isochronous endpoint (bulk, control, interrupt)
CTR events. 0 is the highest priority.
IEE
7
PIECE
2
PIECE
1
PIECE
0
NIEE
PNIEN
2
PNIEN
1
PNIEN
0
0