ST92T163 ST Microelectronics, ST92T163 Datasheet - Page 47

• Manufacturer Part Number: ST92T163
• Description: 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS
• Manufacturer: ST Microelectronics

INTERRUPTS (Cont’d)
3.2 INTERRUPT VECTORING
The ST9 implements an interrupt vectoring struc-
ture which allows the on-chip peripheral to identify
the location of the first instruction of the Interrupt
Service Routine automatically.
When an interrupt request is acknowledged, the
peripheral interrupt module provides, through its
Interrupt Vector Register (IVR), a vector to point
into the vector table of locations containing the
start addresses of the Interrupt Service Routines
(defined by the programmer).
Each peripheral has a specific IVR mapped within
its Register File pages.
The Interrupt Vector table, containing the address-
es of the Interrupt Service Routines, is located in
the first 256 locations of Memory pointed to by the
ISR register, thus allowing 8-bit vector addressing.
For a description of the ISR register refer to the
chapter describing the MMU.
The user Power on Reset vector is stored in the
first two physical bytes in memory, 000000h and
000001h.
Figure 20. Interrupt Vector Table
R240
R239
INT. VECTOR REGISTER
F PAGE REGISTE RS
REGISTE R FILE
EVEN
ODD
000000h
000004h
0000FFh
000002h
USER DIVIDE-BY -ZERO ISR
LO
HI
LO
HI
LO
HI
LO
HI
The Top Level Interrupt vector is located at ad-
dresses 0004h and 0005h in the segment pointed
to by the Interrupt Segment Register (ISR).
With one Interrupt Vector register, it is possible to
address several interrupt service routines; in fact,
peripherals can share the same interrupt vector
register among several interrupt channels. The
most significant bits of the vector are user pro-
grammable to define the base vector address with-
in the vector table, the least significant bits are
controlled by the interrupt module, in hardware, to
select the appropriate vector.
Note: The first 256 locations of the memory seg-
ment pointed to by ISR can contain program code.
3.2.1 Divide by Zero trap
The Divide by Zero trap vector is located at ad-
dresses 0002h and 0003h of each code segment;
it should be noted that for each code segment a
Divide by Zero service routine is required.
Warning . Although the Divide by Zero Trap oper-
ates as an interrupt, the FLAG Register is not
pushed onto the system Stack automatically. As a
result it must be regarded as a subroutine, and the
service routine must end with the RET instruction
(not IRET ).
USER MAIN PROGRAM
USER TOP LEVEL ISR
PROGRAM MEMORY
POWER-ON RESET
DIVIDE-B Y-ZERO
TOP LEVEL INT.
ISR ADDRES S
USER ISR
ST92163 - INTERRUPTS
VECTOR
TABLE
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