ST92T163 ST Microelectronics, ST92T163 Datasheet - Page 178

• Manufacturer Part Number: ST92T163
• Description: 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS
• Manufacturer: ST Microelectronics

ST92163 - I2C BUS INTERFACE
I2C INTERFACE (Cont’d)
Figure 83. I
Any transfer can be done using either the I
registers directly or via the DMA.
If the transfer is to be done directly on I
interface waits (by holding the SCL line low) for
software to write in the Data Register before
transmission of a data byte, or to read the Data
Register after a data byte is received.
If the transfer is to be done via DMA, the interface
sends a request for a DMA transfer. Then it waits
for the DMA to complete. The transfer between the
interface and the I
rising edge of the SCL clock.
The SCL frequency (F
mode is controlled by a programmable clock divid-
er. The speed of the I
between Standard (0-100KHz) and Fast (100-
400KHz) I
8.5.4 I
To enable the interface in I
bit must be set twice as the first write only acti-
vates the interface (only the PE bit is set); and the
bit7 of I2CCR register must be cleared.
The I
(the M/SL bit is cleared) except when it initiates a
transmission or a receipt sequencing (master
mode).
178/224
2
2
C interface always operates in slave mode
C State Machine
2
C modes.
2
SCL
SDA
C BUS Protocol
CONDITION
START
2
C bus will begin on the next
2
C interface may be selected
scl
) generated in master
2
C mode the I2CCR.PE
MSB
1
2
2
C, the
2
C
The multimaster function is enabled with an auto-
matic switch from master mode to slave mode
when the interface loses the arbitration of the I
bus.
8.5.4.1 I
As soon as a start condition is detected, the
address word is received from the SDA line and
sent to the shift register; then it is compared with
the address of the interface or the General Call
address (if selected by software).
Note: In 10-bit addressing mode, the comparison
includes the header sequence (11110xx0) and the
two most significant bits of the address.
Header (10-bit mode) or Address (both 10-bit
and 7-bit modes) not matched: the state
machine is reset and waits for another Start
condition.
Header matched (10-bit mode only): the
interface generates an acknowledge pulse if the
ACK bit of the control register (I2CCR) is set.
Address matched: the I2CSR1.ADSL bit is set
and an acknowledge bit is sent to the master if
the I2CCR.ACK bit is set. An interrupt is sent to
the microcontroller if the I2CCR.ITE bit is
set.Then it waits for the microcontroller to read
the I2CSR1 register by holding the SCL line
low (see Figure 84 Transfer sequencing EV1).
2
8
C Slave Mode
ACK
9
CONDITION
STOP
VR02119B
2
C