MC9S08GB32 Motorola, MC9S08GB32 Datasheet - Page 216

• Manufacturer Part Number: MC9S08GB32
• Description: Microcontrollers
• Manufacturer: Motorola

Inter-Integrated Circuit (IIC) Module
RSTA — Repeat START
13.5.4
TCF — Transfer Complete Flag
IAAS — Addressed as a Slave
BUSY — Bus Busy
ARBL — Arbitration Lost
216
Writing a one to this bit will generate a repeated START condition provided it is the current master.
This bit will always be read as a low. Attempting a repeat at the wrong time will result in loss of
arbitration.
This bit is set on the completion of a byte transfer. Note that this bit is only valid during or immediately
following a transfer to the IIC module or from the IIC module.The TCF bit is cleared by reading the
IIC1D register in receive mode or writing to the IIC1D in transmit mode.
The IAAS bit is set when its own specific address is matched with the calling address. Writing the
IIC1C register clears this bit.
The BUSY bit indicates the status of the bus regardless of slave or master mode. The BUSY bit is set
when a START signal is detected and cleared when a STOP signal is detected.
This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be cleared by
software, by writing a one to it.
1 = Transfer complete.
0 = Transfer in progress.
1 = Addressed as a slave.
0 = Not addressed.
1 = Bus is busy.
0 = Bus is idle.
1 = Loss of arbitration.
0 = Standard bus operation.
IIC Status Register (IIC1S)
Reset:
Read:
Write:
Bit 7
TCF
1
Figure 13-8. IIC Status Register (IIC1S)
= Unimplemented or Reserved
MC9S08GB/GT Data Sheet, Rev. 2.3
IAAS
6
0
BUSY
5
0
ARBL
4
0
3
0
0
SRW
2
0
IICIF
Freescale Semiconductor
1
0
RXAK
Bit 0
0