MC9S08GB32 Motorola, MC9S08GB32 Datasheet - Page 231
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MC9S08GB32
Manufacturer Part Number
MC9S08GB32
Description
Microcontrollers
Manufacturer
Motorola
Datasheet
1.MC9S08GB32.pdf
(290 pages)
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RES8 — ATD Resolution Select
SGN — Signed Result Select
PRS — Prescaler Rate Select
Freescale Semiconductor
This bit determines the resolution of the ATD converter, 8-bits or 10-bits. The ATD converter has the
accuracy of a 10-bit converter. However, if 8-bit compatibility is required, selecting 8-bit resolution
will map result data bits 9-2 onto ATD1RH bits 7-0.
The effect of the RES8 bit on the result is shown in
This bit determines whether the result will be signed or unsigned data. Signed data is represented as
2’s complement data and is achieved by complementing the MSB of the result. Signed data mode can
be used only when the result is left justified (DJM = 0) and is not available for right-justified mode
(DJM = 1). When a signed result is selected, the range for conversions becomes –512 ($200) to 511
($1FF) for 10-bit resolution and –128 ($80) to 127 ($7F) for 8-bit resolution.
The effect of the SGN bit on the result is shown in
This field of bits determines the prescaled factor for the ATD conversion clock.
the divide-by operation and the appropriate range of bus clock frequencies.
1 = 8-bit resolution selected.
0 = 10-bit resolution selected.
1 = Left justified result data is signed.
0 = Left justified result data is unsigned.
RES8
1
2
1
1
1
0
0
0
The SGN bit is only effective when DJM = 0. When DJM = 1, SGN is ignored.
8-bit results are always in ATD1RH.
DJM
0
0
1
0
0
1
SGN
X
X
0
1
0
1
1
1
Table 14-3. Available Result Data Formats
MC9S08GB/GT Data Sheet, Rev. 2.3
10-bit : right justified : unsigned
10-bit : left justified : unsigned
8-bit : left justified
8-bit : left justified : unsigned
10-bit : left justified : signed
8-bit : left justified : signed
Data Formats of Result
2
Table
Table
: unsigned
14-3.
14-3.
V
REFH
$FF:$C0
$7F:$C0
$FF:$00
$7F:$00
$FF:$00
$03:$FF
V
ATD1RH:ATD1RL
DDA
= V
Analog Input
DDA
ATD Registers and Control Bits
, V
Table 14-4
REFL
$00:$00
$80:$00
$00:$00
$00:$00
$80:$00
$00:$00
V
SSA
= V
SSA
illustrates
231
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