MC9S08GB32 Motorola, MC9S08GB32 Datasheet - Page 89

• Manufacturer Part Number: MC9S08GB32
• Description: Microcontrollers
• Manufacturer: Motorola

PTCDDn — Data Direction for Port C Bit n (n = 0–7)
6.6.4
Port D includes eight pins shared between general-purpose I/O, TPM1, and TPM2. Port D pins used as
general-purpose I/O pins are controlled by the port D data (PTDD), data direction (PTDDD), pullup enable
(PTDPE), and slew rate control (PTDSE) registers.
If a TPM takes control of a port D pin, the corresponding PTDDD bit is ignored. When the TPM is in
output compare mode, the corresponding PTDSE can be used to provide slew rate on the pin. When the
TPM is in input capture mode, the corresponding PTDPE can be used, provided the corresponding
PTDDD bit is 0, to provide a pullup device on the pin.
Reads of PTDD will return the logic value of the corresponding pin, provided PTDDD is 0.
Freescale Semiconductor
These read/write bits control the direction of port C pins and what is read for PTCD reads.
PTDD
PTDPE
PTDSE
PTDDD
1 = Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn.
0 = Input (output driver disabled) and reads return the pin value.
Port D Registers (PTDD, PTDPE, PTDSE, and PTDDD)
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PTDDD7 PTDDD6 PTDDD5 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0
PTDPE7
PTDSE7
PTDD7
Bit 7
0
0
0
0
PTDPE6
PTDSE6
MC9S08GB/GT Data Sheet, Rev. 2.3
PTDD6
Figure 6-12. Port D Registers
6
0
0
0
0
PTDPE5
PTDSE5
PTDD5
5
0
0
0
0
PTDPE4
PTDSE4
PTDD4
4
0
0
0
0
PTDPE3
PTDSE3
PTDD3
3
0
0
0
0
PTDPE2
PTDSE2
PTDD2
Parallel I/O Registers and Control Bits
2
0
0
0
0
PTDPE1
PTDSE1
PTDD1
1
0
0
0
0
PTDPE0
PTDSE0
PTDD0
Bit 0
0
0
0
0
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