K9F1G08Q0M-PCB0 Samsung semiconductor, K9F1G08Q0M-PCB0 Datasheet
K9F1G08Q0M-PCB0
Related parts for K9F1G08Q0M-PCB0
K9F1G08Q0M-PCB0 Summary of contents
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... Gb 1.8V NAND Flash Errata Description : Some of AC characteristics are not meeting the specification. > AC characteristics : Refer to Table Affected Products : K9F1G08Q0M-YCB0/YIB0, K9F1G16Q0M-YCB0/YIB0 K9K2G08Q0M-YCB0/YIB0, K9K2G16Q0M-YCB0/YIB0 Improvement schedule : The components targeted to meet the specification Workaround : Relax the relevant timing parameters according to the table. Table ...
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... K9F1GXXQ0M : Vcc 1.65V~1.95V --> 1.70V~1.95V Pb-free Package is added. 0.6 K9F1G08U0M-FCB0,FIB0 K9F1G08Q0M-PCB0,PIB0 K9F1G08U0M-PCB0,PIB0 K9F1G16U0M-PCB0,PIB0 K9F1G16Q0M-PCB0,PIB0 The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 Document Title 128M x 8 Bit / 64M x 16 Bit Revision History Revision No History 0.7 Errata is added.(Front Page)-K9F1GXXQ0M Specification Relaxed value 1. The 3rd Byte ID after 90h ID read command is don’ t cared. 0.8 The 5th Byte ID after 90h ID read command is deleted. ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 128M x 8 Bit / 64M x 16 Bit NAND Flash Memory PRODUCT LIST Part Number K9F1G08Q0M-Y,P K9F1G16Q0M-Y,P K9F1G08U0M-Y,P K9F1G16U0M-Y,P K9F1G08U0M-V,F FEATURES Voltage Supply -1.8V device(K9F1GXXQ0M): 1.70V~1.95V -3.3V device(K9F1GXXU0M): 2.7 V ~3.6 V Organization - Memory Cell Array -X8 device(K9F1G08X0M) : (128M + 4,096K)bit x 8bit -X16 device(K9F1G16X0M) : (64M + 2,048K)bit x 16bit ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 PIN CONFIGURATION (TSOP1) X16 X8 N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C R/B R N.C N.C N.C N.C Vcc Vcc Vss Vss N.C N.C N.C N.C CLE CLE ALE ALE N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE( TSOP1 - 1220F #1 #24 ¡Æ 0~8 0.45~0.75 0.018~0.030 K9F1GXXX0M-YCB0,PCB0/YIB0,PIB0 ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 PIN CONFIGURATION (WSOP1) N.C N.C DNU N.C N.C N.C R DNU N.C Vcc Vss N.C DNU CLE ALE WE WP N.C N.C DNU N.C N.C PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE ( WSOP1 - 1217F #1 #24 K9F1G08U0M-VCB0,FCB0/VIB0,FIB0 ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS I/O ~ I/O The I/O pins are used to input command, address and data, and to output data during read operations. The (K9F1G08X0M) O pins float to high-z when the chip is deselected or when the outputs are disabled. ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 Figure 1-1. K9F1G08X0M (X8) Functional Block Diagram Command CE Control Logic RE & High Voltage WE CLE Figure 2-1. K9F1G08X0M (X8) Array Organization 64K Pages (=1,024 Blocks) 2K Bytes Page Register I/O 0 1st Cycle A 0 2nd Cycle A 8 3rd Cycle ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 Figure 1-2. K9F1G16X0M (X16) Functional Block Diagram Command CE Control Logic RE & High Voltage WE CLE Figure 2-2. K9F1G16X0M (X16) Array Organization 64K Pages (=1,024 Blocks) 1K Words Page Register I/O 0 I/O 1 1st Cycle 2nd Cycle ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 Product Introduction The K9F1GXXX0M is a 1056Mbit(1,107,296,256 bit) memory organized as 65,536 rows(pages) by 2112x8(X8 device) or 1056x16(X16 device) columns. Spare 64(X8) or 32(X16) columns are located from column address of 2048~2111(X8 device) or 1024~1055(X16 device). A 2112-byte(X8 device) or 1056-word(X16 device) data register and a 2112-byte(X8 device) or 1056- word(X16 device) cache register are serially connected to each other ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative K9F1GXXX0M-XCB0 Temperature Under Bias K9F1GXXX0M-XIB0 K9F1GXXX0M-XCB0 Storage Temperature K9F1GXXX0M-XIB0 Short Circuit Current NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 VALID BLOCK Parameter Valid Block Number NOTE : K9F1GXXX0M 1. The may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 AC Timing Characteristics for Command / Address / Data Input Parameter CLE setup Time CLE Hold Time CE setup Time CE Hold Time WE Pulse Width ALE setup Time ALE Hold Time Data setup Time Data Hold Time Write Cycle Time WE High Hold Time NOTE : 1 ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 NAND Flash Technical Notes Invalid Block(s) Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor- mation regarding the invalid block( called as the invalid block information. Devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 NAND Flash Technical Notes (Continued) Error in write or read operation Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 NAND Flash Technical Notes (Continued) Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Erase Error I Erase Completed : If erase operation results in an error, map out * the failing block and replace it with another block. ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 System Interface Using CE don’ t-care. For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2112byte(X8 device) or 1056word(X16 device) data registers are utilized as separate buffers for this operation and the system design gets more flexible ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 NOTE Device K9F1G08X0B(X8 device) I I/O 7 K9F1G16X0B(X16 device Command Latch Cycle CLE CE WE ALE I/Ox K9F1G16X0M : I must be set to "0" * Address Latch Cycle t CLS CLE ALS ALE I/Ox K9F1G16X0M : I must be set to "0" I/O DATA ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 * Input Data Latch Cycle CLE CE t ALS ALE WE I/Ox * Serial Access Cycle after Read CE t REA RE I/ R/B NOTES : Transition is measured 200mV from steady state voltage with load DIN 0 DIN 1 ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 * Status Read Cycle CLE I/Ox K9F1G16X0M : I must be set to "0" t CLR t CLS t CLH WHR 70h 19 FLASH MEMORY t CEA t CHZ RHZ* t REA t IR Status Output SAMSUNG ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 Read Operation CLE ALE RE I/Ox 00h Col. Add1 Column Address R/B Read Operation (Intercepted by CE) CLE CE WE ALE RE I/Ox 00h Col. Add1 Column Address R 30h Col. Add2 Row Add1 Row Add2 Row Address Col. Add2 Row Add1 ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 FLASH MEMORY 21 SAMSUNG ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 Page Program Operation CLE ALE RE I/Ox Col. Add2 80h Co.l Add1 SerialData Column Address Input Command R Din Din Row Add1 Row Add2 Byte Row Address Serial Input X8 device : m = 2112byte X16 device : m = 1056word ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 FLASH MEMORY 23 SAMSUNG ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 FLASH MEMORY 24 SAMSUNG ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 FLASH MEMORY 25 SAMSUNG ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 BLOCK ERASE OPERATION CLE ALE RE I/Ox 60h Row Add1 Row Address R/B Auto Block Erase Setup Command t t BERS WB Row Add2 D0h Busy Erase Command 26 FLASH MEMORY 70h I/O 0 I/O =0 Successful Erase 0 Read Status I/O =1 Error in Erase 0 Command ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 Read ID Operation CLE CE WE ALE RE I/Ox 90h Read ID Command ID Defintition Table Access command = 90H Description st 1 Byte Maker Code 2 nd Byte Device Code rd Don’ t care 3 Byte Page Size, Block Size, Spare Size, Organization,Serial access minimum ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 4th ID Data 1KB Page Size 2KB (w/o redundant area ) Reserved Reserved 64KB Blcok Size 128KB (w/o redundant area ) 256KB Reserved Redundant Area Size 8 ( byte/512byte Organization x16 50ns 30ns Serial Access minimum Reserved Reserved Description I/O7 I/ ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 Device Operation PAGE READ Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h and 30h to the com- mand register along with four address cycles. In two consecutive read operations, the second one doesn’ t need 00h command, which five address cycles and 30h command initiates that operation ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 Figure 7. Random Data Output In a Page R/B RE Address I/Ox 00h 4Cycles Col Add1,2 & Row Add1,2 PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a word or consecutive bytes up to 2112(X8 device) or words up to 1056(X16 device single page program cycle. The number of consecutive partial ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 Figure 9. Random Data Input In a Page R/B I/Ox 80h Address & Data Input Col Add1,2 & Row Add1,2 Data Cache Program Cache Program is an extension of Page Program, which is executed with 2112byte(X8 device) or 1056word(X16 device) data regis- ters, and is available only within a block. Since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed into memory cell ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after com- pletion of the previous cycle, which can be expressed as the following formula ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 BLOCK ERASE The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup com- mand(60h). Only address Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 Read ID The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Four read cycles sequentially output the manufacturer code(ECh), and the device code and XXh, 4th cycle ID, respectively. The command register remains in Read ID mode until further commands are issued to it ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 Power-On Auto-Read The device is designed to offer automatic reading of the first page without command and address input sequence during power-on. An internal voltage detector enables auto-page read functions when Vcc reaches about 1.8V. PRE pin controls activation of auto- page read function. Auto-page read function is enabled only when PRE pin is tied to V without latency ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...
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... K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0 Data Protection & Power up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device) or 2V(3.3V device). WP pin provides hardware protection and is recommended to be kept at V during power-up and power-down ...