RG82845M Intel, RG82845M Datasheet - Page 121

• Manufacturer Part Number: RG82845M
• Description: Chipset Memory Controller Hub Mobile
• Manufacturer: Intel

250687-002
R
NOTE:
As a target of an AGP FRAME# cycle, the MCH-M only supports the following transactions:
As an initiator of AGP FRAME# cycle, the MCH-M only supports the following transactions:
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and
Invalidate
• Memory Read. Recommended for reads of 32 bytes or less.
• Memory Read Line, and Memory Read Multiple. These commands are supported identically by the
• Memory Write and Memory Write and Invalidate. These commands are aliased and processed
• Other Commands. Other commands such as I/O R/W and Configuration R/W are not supported by
• Exclusive Access. The MCH-M does not support PCI locked cycles as a target.
• Fast Back-to-Back Transactions. MCH-M as a target supports fast back-to-back cycles from an
• Memory Read and Memory Read Line. MCH-M uses these commands to support read requests from
• Memory Read Multiple. This command is not supported by the MCH-M as an AGP FRAME#
• Memory Write. MCH-M initiates AGP FRAME# write cycles on behalf of the host or the hub
• I/O Read and Write. I/O reads and writes from the host are sent to the AGP bus if they fall within
MCH-M and allow the MCH-M to continuously supply data during MRL and MRM burst.
Recommended for reads of more than 32 bytes. The MCH-M does not support reads of the hub
interface bus from AGP.
identically. The MCH-M does not support writes of the hub interface bus from AGP.
the MCH-M as a target and result in master abort.
AGP FRAME# initiator.
host to AGP. MCH-M does not support memory reads from the hub interface to AGP.
initiator.
interface. MCH-M does not issue Memory Write and Invalidate as an initiator. MCH-M does not
support write merging or write collapsing. MCH-M allows non-snoopable write transactions from
the hub interface to the AGP bus.
the I/O base and limit address range for the AGP bus as programmed in the MCH-M’s PCI
configuration registers. All other host-initiated I/O accesses that do not correspond to this
PCI Command
N/A refers to a function that is not applicable.
C/BE[3:0]# Encoding
1001
1010
1011
1100
1100
1101
1110
1110
1111
1111
Datasheet
Intel
®
82845MP/82845MZ Chipset-Mobile (MCH-M)
Cycle Destination
The Hub interface
The Hub interface
The Hub interface
Main Memory
Main Memory
Main Memory
N/A
N/A
N/A
N/A
MCH-M
Response as aFRAME#
No Response
No Response
No Response
No Response
No Response
No Response
No Response
Post Data
Target
Read
Read
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