RG82845M Intel, RG82845M Datasheet - Page 5

• Manufacturer Part Number: RG82845M
• Description: Chipset Memory Controller Hub Mobile
• Manufacturer: Intel

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System Address Map ............................................................................................................... 105
4.1.
4.2.
4.3.
4.4.
4.5.
Functional Description.............................................................................................................. 114
5.1.
5.2.
5.3.
3.8.17.
3.8.18.
3.8.19.
3.8.20.
3.8.21.
3.8.22.
3.8.23.
3.8.24.
Memory Address Ranges ............................................................................................ 105
4.1.1.
4.1.2.
4.1.3.
4.1.4.
4.1.5.
4.1.6.
4.1.7.
4.1.8.
4.1.9.
AGP Memory Address Ranges ................................................................................... 110
4.2.1.
System Management Mode (SMM) Memory Range ................................................... 111
4.3.1.
4.3.2.
I/O Address Space ...................................................................................................... 112
MCH-M Decode Rules and Cross-Bridge Address Mapping ...................................... 112
4.5.1.
4.5.2.
Host Interface Overview .............................................................................................. 114
5.1.1.
5.1.2.
5.1.3.
System Memory Interface ........................................................................................... 115
5.2.1.
5.2.2.
5.2.3.
AGP Interface Overview.............................................................................................. 117
5.3.1.
5.3.2.
5.3.3.
5.3.4.
5.3.5.
5.3.6.
5.2.2.1.
5.2.3.1.
MBASE1 – Memory Base Address Register – Device #1 ........................... 96
MLIMIT1 – Memory Limit Address Register – Device #1............................ 97
PMBASE1 – Prefetchable Memory Base Address Register – Device #1 ... 98
PMLIMIT1 – Prefetchable Memory Limit Address Register – Device #1 .... 99
BCTRL1 – PCI-PCI Bridge Control Register – Device #1 ......................... 100
ERRCMD1 – Error Command Register – Device #1 ................................ 101
DWTMC – DRAM Write Thermal Management Control ........................... 102
DRTMC – DRAM Read Thermal Management Control ............................ 104
VGA and MDA Memory Space.................................................................. 106
PAM Memory Spaces................................................................................ 107
ISA Hole Memory Space ........................................................................... 108
TSEG SMM Memory Space ...................................................................... 108
System Bus Interrupt APIC Memory Space .............................................. 109
High SMM Memory Space ........................................................................ 109
AGP Aperture Space (Device #0 BAR) ..................................................... 109
AGP Memory and Prefetchable Memory................................................... 109
Hub Interface A Subtractive Decode ......................................................... 110
AGP DRAM Graphics Aperture ................................................................. 110
SMM Space Definition............................................................................... 111
SMM Space Restrictions ........................................................................... 112
Decode Rules for the Hub Interface A ...................................................... 112
AGP Interface Decode Rules .................................................................... 113
Dynamic Bus Inversion.............................................................................. 114
System Bus Interrupt Delivery................................................................... 114
Upstream Interrupt Messages................................................................... 115
DDR Interface Overview............................................................................ 115
Memory Organization and Configuration................................................... 116
DRAM Performance Description ............................................................... 117
AGP Target Operations............................................................................. 118
AGP Transaction Ordering........................................................................ 119
AGP Signal Levels .................................................................................... 119
4x AGP Protocol........................................................................................ 119
Fast Writes ................................................................................................ 119
AGP FRAME# Transactions on AGP........................................................ 120
5.2.2.1.1.
5.2.2.1.2.
5.2.2.1.3.
Configuration Mechanism for SO-DIMMs..................................... 116
Data Integrity (ECC) ..................................................................... 117
Datasheet
Memory Detection and Initialization............................ 116
SMBus Configuration and Access of the Serial
Presence Detect Ports................................................ 116
Memory Register Programming ................................. 116
Intel
®
82845MP/82845MZ Chipset-Mobile (MCH-M)
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