RG82845M Intel, RG82845M Datasheet - Page 58

• Manufacturer Part Number: RG82845M
• Description: Chipset Memory Controller Hub Mobile
• Manufacturer: Intel

Intel
3.7.14.
3.7.15.
58
®
82845MP/82845MZ Chipset-Mobile (MCH-M)
Offset:
Offset:
AGPM- AGP Miscellaneous Configuration
Default:
Access:
Size:
DRB[0:7] – DRAM Row Boundary Registers – Device #0
Default:
Access:
Size:
The DRAM Row Boundary Register defines the upper boundary address of each pair of DRAM rows
with a granularity of 32 MB. Each row has its own single-byte DRB register. For example, a value of 1
in DRB0 indicates that 32 MB of DRAM has been populated in the first row.
Row0:
Row1:
Row2:
Row3:
Row4:
Row5:
Row6:
Row7:
DRB0 = Total memory in row0 (in 32MB increments)
DRB1 = Total memory in row0 + row1 (in 32MB increments)
----
DRB3 = Total memory in row0 + row1 + row2 + row3 (in 32MB increments)
** When in DDR mode DRB[4:7] must be programmed with value contained in DRB3.
Each Row is represented by a byte. Each byte has the following format.
7:2
1
0
7:0
Bit
Bit
60h
61h
62h
63h
64h **
65h **
66h **
67h **
Reserved
Aperture Access Global Enable (APEN): This bit is used to prevent access to the graphics aperture
from any port (CPU, HI_A, or AGP/PCI_B) before the aperture range is established by the
configuration software and the appropriate translation table in the main DRAM has been initialized.
The default value is "0", so this field must be set after system is fully configured in order to enable
aperture accesses.
Reserved
DRAM Row Boundary Address: This 8-bit value defines the upper and lower addresses for each
DRAM row. This 8-bit value is compared against a set of address lines to determine the upper
address limit of a particular row.
51h
00h
Read/Write
8 bits
60-67h
00h
Read/Write
8 bits
Datasheet
Description
Description
250687-002
R