RG82845M Intel, RG82845M Datasheet - Page 89

• Manufacturer Part Number: RG82845M
• Description: Chipset Memory Controller Hub Mobile
• Manufacturer: Intel

3.8.4.
250687-002
R
Address Offset:
PCISTS1 – PCI-PCI Status Register – Device #1
Default Value:
Access:
Size:
PCISTS1 is a 16-bit status register that reports the occurrence of error conditions associated with primary
side of the “virtual” PCI-PCI bridge embedded within the MCH-M. Since this device does not
physically reside on PCI_A it reports the optimum operating conditions so that it does not restrict the
capability of PCI_A.
10:9
4:0
Bit
15
14
13
12
11
8
7
6
5
Detected Parity Error (DPE1): Not Applicable - hardwired to “0.”
Signaled System Error (SSE1): This bit is set to 1 when MCH-M Device #1 generates an SERR
message over the hub interface A for any enabled Device #1 error condition. Device #1 error
conditions are enabled in the ERRCMD, PCICMD1 and BCTRL1 registers. Device #1 error flags are
read/reset from the ERRSTS and SSTS1 register. Software clears this bit by writing a 1 to it.
Received Master Abort Status (RMAS1): Not Applicable - hardwired to “0.”
Received Target Abort Status (RTAS1): Not Applicable - hardwired to “0.”
Signaled Target Abort Status (STAS1): Not Applicable - hardwired to “0.”
DEVSEL# Timing (DEVT1): This bit field is hardwired to “00b” to indicate that the device #1 uses the
fastest possible decode.
Data Parity Detected (DPD1): Not Applicable - hardwired to “0”.
Fast Back-to-Back Capable (FB2B1): This bit is hardwired to “1” to indicate that the AGP port
supports fast back to back transactions when the transactions are to different targets.
Reserved
66-MHz Capability (CAP66): This bit is hardwired to “1” to indicate that the AGP port is 66-MHz
capable.
Reserved
06-07h
00A0h
Read Only, Read/Write Clear
16 bits
Datasheet
Intel
®
Descriptions
82845MP/82845MZ Chipset-Mobile (MCH-M)
89