K7D801871B-HC30 Samsung semiconductor, K7D801871B-HC30 Datasheet - Page 12

• Manufacturer Part Number: K7D801871B-HC30
• Description: 256Kx36 & 512Kx18 SRAM
• Manufacturer: Samsung semiconductor

K7D803671B
K7D801871B
K
K
B1
B2
B3
SA
G
DQ
CQ
CQ
NOP
Q
t
X1
1
CHQZ
NOTE :
1. Q
2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present.
3. This devices supports cycle lengths of 1, 2, 4. Continue(B1=HIGH, B2=HIGH, B3=X) up to three times following a B1 operation. Any further
4. This device will have an address wraparound if further Continues are applied.
t
t
BVKH
AVKH
Continue assertions constitute invalid operations.
t
01
KHKH
refers to output from address A
READ
(burst of 4)
A
2
0
t
t
TIMING WAVEFORMS FOR SINGLE DATA RATE CYCLES
KXCH
KHKL
t
t
KHBX
KHAX
t
t
CHQV
KLKH
t
CHLZ
READ
CONTINUE
3
Q
READ
CONTINUE
4
01
0
. Q
t
CHQX
02
refers to output from the next internal burst address following A
(Burst Length=4, 2, 1)
Q
READ
CONTINUE
02
5
Q
03
READ
(burst of 1)
A
6
1
- 12
NOP
Q
7
04
t
t
GHQX
GHQZ
Q
NOP
11
8
256Kx36 & 512Kx18 SRAM
WRITE
(burst of 2)
9
A
2
t
DVKH
WRITE
CONTINUE
D
10
0
21
, etc.
t
DON’ T CARE
KHDX
11
D
READ
(burst of 2)
A
22
3
t
t
GLQV
GLQX
January. 2002
UNDEFINED
READ
CONTINUE
12
Rev 4.0
Q
31