K7D801871B-HC30 Samsung semiconductor, K7D801871B-HC30 Datasheet - Page 2

• Manufacturer Part Number: K7D801871B-HC30
• Description: 256Kx36 & 512Kx18 SRAM
• Manufacturer: Samsung semiconductor

K7D803671B
K7D801871B
FEATURES
• 256Kx36 or 512Kx18 Organizations.
• Maximum Frequency : 370MHz (Data Rate : 740Mbps)
• 2.5V V
• HSTL Input and Outputs.
• Single Differential HSTL Clock.
• Synchronous Pipeline Mode of Operation with Self-Timed Late Write.
• Free Running Active High and Active Low Echo Clock Output Pin.
• Asynchronous Output Enable.
• Registered Addresses, Burst Control and Data Inputs.
• Registered Outputs.
• Single and Double Data Rate Burst Read and Write.
• Burst Count Controllable With Max Burst Length of 4
• Interleved and Linear Burst mode support
• Bypass Operation Support
• Programmable Impedance Output Drivers.
• JTAG Boundary Scan (subset of IEEE std. 1149.1)
• 153(9x17) Pin Ball Grid Array Package(14mm x 22mm).
SA[0:17]( or SA[0:18])
K,K
B
B
B
G
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
1
3
2
Pin Name
SA
CQ, CQ
LBO
K, K
DQ
SA
0
DD
B
B
B
G
, SA
Synchronous
R/W control
Internal
Clock
Generator
1
2
3
/1.5V V
SD/DD
Advance
Control
Co
Select
Clock
Buffer
1
&
DDQ
Differential Clocks
Synchronous Address Input
Synchronous Burst Address Input (SA
Synchronous Data I/O
Differential Output Echo Clocks
Load External Address
Burst R/W Enable
Single/Double Data Selection
Asynchronous Output Enable
Linear Burst Order
(2.0V max V
CE
CE
Address
Register
Write
Address
Register
(2 stage)
CE
R/W
LD
DDQ
Pin Description
Comparator
).
Data Output Strobe
Data Output Enable
State Machine
18(or 19)
18(or 19)
Strobe_out
(Burst Write
(Burst Address)
Address)
16(or 17)
Burst
Counter
0
16(or 17)
= LSB)
- 2 -
NOTE : *Access time equals
Organization
256Kx36
512Kx18
MUX
Pin Name
2:1
V
TMS
TDO
V
TCK
V
V
TDI
ZQ
NC
DDQ
REF
DD
SS
Dec.
256Kx36 & 512Kx18 SRAM
K7D803671B-HC37
K7D803671B-HC35
K7D803671B-HC33
K7D803671B-HC30
K7D803671B-HC25
K7D801871B-HC37
K7D801871B-HC35
K7D801871B-HC33
K7D801871B-HC30
K7D801871B-HC25
Output Driver Impedance Control Input
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
HSTL Input Reference Voltage
Power Supply
Output Power Supply
GND
No Connection
Part Number
JTAG Test Data Output
Data Out
2 : 1 MUX
S/A Array
Output
Buffer
t
KXCH/
DQ
36(or 18)
36(or 18)x2
36(or 18)x2
t
Pin Description
KXCL
Memory Array
Echo Clock
(512Kx18)
256Kx36
Output
Frequency
Maximum
or
370MHz
357MHz
333MHz
300MHz
250MHz
370MHz
357MHz
333MHz
300MHz
250MHz
CQ,CQ
January. 2002
Write Buffer
(2 stage)
Register
Data In
Access
Data In
36(or18)x2
36(or18)x2
W/D
Array
XDIN
Time
Rev 4.0
1.7*
1.7*
1.7*
1.9*
2.0*
1.7*
1.7*
1.7*
1.9*
2.0*