K7D801871B-HC30 Samsung semiconductor, K7D801871B-HC30 Datasheet - Page 13

• Manufacturer Part Number: K7D801871B-HC30
• Description: 256Kx36 & 512Kx18 SRAM
• Manufacturer: Samsung semiconductor

K7D803671B
K7D801871B
TAP Controller State Diagram
The SRAM provides a limited set of IEEE standard 1149.1 JTAG functions. This is to test the connectivity during manufacturing
between SRAM, printed circuit board and other components. Internal data is not driven out of SRAM under JTAG control. In conform-
ance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP control-
ler has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use
this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM. TCK must
be tied to V
application of a logic 1, and may be left unconnected. But they may also be tied to V
nected.
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
JTAG Block Diagram
TMS
TCK
TDI
SA
SS
to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the
1
0
Test Logic Reset
BYPASS Reg.
Identification Reg.
Instruction Reg.
Control Signals
Run Test Idle
TAP Controller
SRAM
CORE
0
1
1
1
1
SA
TDO
Capture DR
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Update DR
Pause DR
Select DR
Exit1 DR
Exit2 DR
Shift DR
0
JTAG Instruction Coding
NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of other
2. TDI is sampled as an input to the first ID register to allow for the serial
3. Bypass register is initiated to V
4. SAMPLE instruction dose not places DQs in Hi-Z.
IR2 IR1 IR0 Instruction
The Bypass Register also holds serially loaded TDI when exiting
the Shift DR states.
0
0
0
0
1
1
1
1
SRAM inputs.
shift of the external TDI data.
invoked.
0
1
0
1
1
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
256Kx36 & 512Kx18 SRAM
DD
EXTEST
IDCODE
SAMPLE-Z Boundary Scan Register
BYPASS
SAMPLE
BYPASS
BYPASS
BYPASS
through a resistor. TDO should be left uncon-
1
1
SS
Boundary Scan Register
Identification Register
Bypass Register
Boundary Scan Register
Bypass Register
Bypass Register
Bypass Register
Capture IR
Update IR
Select IR
Pause IR
when BYPASS instruction is
Exit1 IR
Exit2 IR
Shift IR
0
TDO Output
1
0
1
0
1
1
0
0
0
0
January. 2002
1
Rev 4.0
Notes
1
2
1
3
4
3
3
3