EVAL-ADUC836QS AD [Analog Devices], EVAL-ADUC836QS Datasheet - Page 12

• Manufacturer Part Number: EVAL-ADUC836QS
• Description: MicroConverter, Dual 16-Bit ADCs with Embedded 62 kB Flash MCU
• Manufacturer: AD [Analog Devices]

52-Lead 56-Lead
MQFP
40
41
42
43–46
49–52
*I = Input, O = Output, S = Supply.
ADuC836
Pin No. Pin No.
CSP
43
44
45
46–49
52–55
Mnemonic
ALE
P0.0–P0.7
(AD0–AD3)
Type* Description
I/O
O
O
I/O
PIN FUNCTION DESCRIPTIONS (continued)
External Access En able, Logic Input. When held high, this input enables the de vice to
fetch code from internal program memory locations 0000h to F7FFh. When held low,
this input enables the device to fetch all in struc tions from ex ter nal program memory.
To de ter mine the mode of code ex e cu tion, i.e., in ter nal or external, the
sampled at the end of an ex ter nal RE SET as ser tion or as part of a device power cycle.
at this pin must not be changed dur ing nor mal mode op er a tion as it may cause an
emulation interrupt that will halt code execution.
Program Store Enable, Logic Output. This output is a control signal that enables the
external program memory to the bus during external fetch op er a tions. It is active every
six oscillator periods except dur ing ex ter nal data mem o ry accesses. This pin remains
high during internal program ex e cu tion.
Download mode when pulled low through a resistor at the end of an external RESET
assertion or as part of a device power cycle.
Address Latch Enable, Logic Output. This output is used to latch the low byte (and
page byte for 24-bit data address space accesses) of the address to external mem o ry
during external code or data memory access cycles. It is activated every six oscillator
periods except during an ex ter nal data mem o ry access. It can be disabled by setting
the PCON.4 bit in the PCON SFR.
These pins are part of Port 0, which is an 8-bit, open-drain, bi di rec tion al
I/O port. Port 0 pins that have 1s written to them fl oat and in that state can be used
(AD4–AD7)as high im ped ance inputs. An external pull-up resistor will be required
on P0 outputs to force a valid logic high level ex ter nal ly. Port 0 is also the mul ti plexed
low order address and data bus dur ing ac cess es to external pro gram or data mem o ry.
In this application, it uses strong internal pull-ups when emitting 1s.
may also be used as an external emulation I/O pin, and therefore the voltage level
–12–
can also be used to enable Serial
pin is
REV. 0