EVAL-ADUC836QS AD [Analog Devices], EVAL-ADUC836QS Datasheet - Page 63

• Manufacturer Part Number: EVAL-ADUC836QS
• Description: MicroConverter, Dual 16-Bit ADCs with Embedded 62 kB Flash MCU
• Manufacturer: AD [Analog Devices]

ADuC836 HARDWARE DESIGN CONSIDERATIONS
This section outlines some of the key hardware design con sid er -
ations that must be addressed when integrating the ADuC836
into any hardware system.
External Memory Interface
In addition to its internal program and data memories, the
ADuC836 can access up to 64 Kbytes of external program mem o ry
(ROM, PROM, and so on) and up to 16 Mbytes of ex ter nal data
memory (SRAM).
To select from which code space (internal or external program
memory) to begin executing code, tie the
pin high or low, respectively. When
user program execution will start at Address 0 in the in ter nal
62 Kbytes Flash/EE code space. When
user program execution will start at Address 0 in the external
code space. When executing from internal code space, accesses
to the program space above F7FFH (62 Kbytes) will be read as
NOP instructions.
Note that a second very important function of the
described in the Single Pin Emulation Mode section.
External program memory (if used) must be connected to the
ADuC836, as illustrated in Figure 58. Sixteen I/O lines (Ports 0
and 2) are dedicated to bus functions during external program
mem o ry fetches. Port 0 (P0) serves as a multiplexed address/data
bus. It emits the low byte of the program counter (PCL) as
an address, and then goes into a high impedance input state
await ing the arrival of the code byte from the program mem o ry.
Dur ing the time that the low byte of the program counter is valid
on P0, the signal ALE (Address Latch Enable) clocks this byte
into an ex ter nal address latch. Meanwhile, Port 2 (P2) emits the
high byte of the program counter (PCH), and
EPROM and the code byte is read into the ADuC836.
Note that program memory addresses are always 16 bits wide,
even in cases where the actual amount of program mem o ry used
is less than 64 Kbytes. External program ex e cu tion sac ri fi c es
two of the 8-bit ports (P0 and P2) to the func tion of ad dress ing
the program memory. While executing from ex ter nal program
mem o ry, Ports 0 and 2 can be used si mul ta neous ly for read/write
access to external data memory, but not for gen er al-pur pose I/O.
REV. 0
Figure 58. External Program Memory Interface
ADuC836
ALE
P0
P2
LATCH
is high (pulled up to V
is low (tied to ground)
D0–D7
(INSTRUCTION)
A0–A7
A8–A15
(external access)
EPROM
strobes the
pin is
DD
),
–63–
Though both external program memory and external data mem o ry
are accessed using some of the same pins, the two are completely
independent of each other from a software point of view. For
example, the chip can read/write external data mem o ry while
executing from external program memory.
Figure 59 shows a hardware confi guration for accessing up to
64 Kbytes of external data memory. This interface is standard to
any 8051 compatible MCU.
If access to more than 64 Kbytes of RAM is desired, a feature
unique to the MicroConverter allows addressing up to 16 Mbytes
of external RAM simply by adding an additional latch, as il lus -
trat ed in Figure 60.
In either implementation, Port 0 (P0) serves as a multiplexed
address/data bus. It emits the low byte of the data pointer (DPL)
as an address, which is latched by ALE prior to data being placed
on the bus by the ADuC836 (write operation) or by the external
data memory (read operation). Port 2 (P2) pro vides the data
pointer page byte (DPP) to be latched by ALE, fol lowed by the
data pointer high byte (DPH). If no latch is con nect ed to P2,
DPP is ignored by the SRAM, and the 8051 standard of 64 Kbyte
external data memory access is main tained.
Detailed timing diagrams of external program and data memory
read and write access can be found in the Timing Specifi cations
section.
Figure 59. External Data Memory Interface
(64 Kbytes Address Space)
Figure 60. External Data Memory Interface
(16 Mbytes Address Space)
ADuC836
ADuC836
ALE
ALE
P2
P2
P0
P0
LATCH
LATCH
LATCH
A0–A7
D0–D7
(DATA)
A0–A7
A8–A15
A16–A23
D0–D7
(DATA)
A8–A15
ADuC836
SRAM
SRAM