EVAL-ADUC836QS AD [Analog Devices], EVAL-ADUC836QS Datasheet - Page 44

• Manufacturer Part Number: EVAL-ADUC836QS
• Description: MicroConverter, Dual 16-Bit ADCs with Embedded 62 kB Flash MCU
• Manufacturer: AD [Analog Devices]

Bit
7
6
5
4
3
2
1
0
*The CPOL and CPHA bits should both contain the same values for master and slave devices.
SERIAL PERIPHERAL INTERFACE
The ADuC836 integrates a complete hardware Serial Peripheral
Interface (SPI) interface on-chip. SPI is an industry-standard
synchronous serial interface that allows eight bits of data to be
synchronously transmitted and received si mul ta neous ly, i.e., full-
duplex. It should be noted that the SPI pins SCLOCK and MOSI
are multiplexed with the I
are controlled via the I2CCON SFR only if SPE is clear. SPI can
be con fi g ured for mas ter or slave op er a tion and typ i cal ly con sists of
four pins:
SCLOCK (Serial Clock I/O Pin), Pin 26
The master clock (SCLOCK) is used to synchronize the data
being transmitted and received through the MOSI and MISO
data lines. A single data bit is transmitted and received in each
SCLOCK period. Therefore, a byte is transmitted/received after
eight SCLOCK periods. The SCLOCK pin is confi gured as an
output in master mode and as an input in Slave mode. In Master
mode, the bit rate, polarity, and phase of the clock are controlled
by the CPOL, CPHA, SPR0, and SPR1 bits in the SPICON SFR
(see Table XXI). In Slave mode, the SPICON reg is ter will have
to be confi gured with the phase and polarity (CPHA and CPOL)
as the master, as for both Master and Slave modes the data is
transmitted on one edge of the SCLOCK signal and sampled on
the other.
ADuC836
Name
ISPI
WCOL
SPE
SPIM
CPOL*
CPHA*
SPR1
SPR0
Description
SPI Interrupt Bit.
Set by MicroConverter at the end of each SPI transfer.
Cleared directly by user code or indirectly by reading the SPIDAT SFR.
Write Col li sion Error Bit.
Set by MicroConverter if SPIDAT is written to while an SPI transfer is in progress.
Cleared by user code.
SPI Interface Enable Bit.
Set by user to enable the SPI interface.
Cleared by user to enable the I
SPI Master/Slave Mode Select Bit.
Set by user to enable Mas ter mode operation (SCLOCK is an output).
Cleared by user to enable Slave mode operation (SCLOCK is an input).
Clock Po lar i ty Select Bit.
Set by user if SCLOCK idles high.
Cleared by user if SCLOCK idles low.
Clock Phase Select Bit.
Set by user if leading SCLOCK edge is to transmit data.
Cleared by user if trailing SCLOCK edge is to transmit data.
SPI Bit Rate Select Bits.
These bits select the SCLOCK rate (bitrate) in Master mode as follows:
SPR1
0
0
1
1
In SPI Slave mode, i.e., SPIM = 0, the logic level on the external
2
C pins SCLOCK and SDATA. The pins
SPR0
0
1
0
1
Table XXI. SPICON SFR Bit Designations
Selected Bit Rate
f
f
f
f
CORE
CORE
CORE
CORE
/2
/4
/8
/16
2
C interface.
–44–
MISO (Master In, Slave Out Data I/O Pin), Pin 14
The MISO (master in slave out) pin is confi gured as an input line
in Master mode and an output line in Slave mode. The MISO
line on the master (data in) should be connected to the MISO
line in the slave device (data out). The data is transferred as byte-
wide (8-bit) serial data, MSB fi rst.
MOSI (Master Out, Slave In Pin), Pin 27
The MOSI (master out slave in) pin is confi gured as an output
line in Master mode and an input line in Slave mode. The MOSI
line on the master (data out) should be connected to the MOSI
line in the slave device (data in). The data is transferred as byte-
wide (8-bit) serial data, MSB fi rst.
The Slave Select (
is confi gured in SPI Slave mode. This line is active low. Data is
only received or transmitted in Slave mode when the
allowing the ADuC836 to be used in single master, multislave SPI
confi gurations. If CPHA = 1, the
pulled low. With CPHA = 0, the
before the fi rst bit in a byte wide trans mis sion or reception and
return high again after the last bit in that byte-wide transmission or
reception. In SPI Slave mode, the logic level on the external
(Pin 13) can be read via the SPR0 bit in the SPICON SFR.
The following SFR registers are used to control the SPI in ter face.
(Slave Select Input Pin), Pin 13
) input pin is only used when the ADuC836
pin (Pin 13), can be read via the SPR0 bit.
input must be driven low
input may be permanently
pin is low,
REV. 0
pin