EVAL-ADUC836QS AD [Analog Devices], EVAL-ADUC836QS Datasheet - Page 50

• Manufacturer Part Number: EVAL-ADUC836QS
• Description: MicroConverter, Dual 16-Bit ADCs with Embedded 62 kB Flash MCU
• Manufacturer: AD [Analog Devices]

P1.2 to P1.7
The remaining Port 1 pins (P1.2 to P1.7) can only be confi gured as
analog input (ADC) or digital input pins. By (power-on) default,
these pins are confi gured as analog inputs, i.e., 1 writ ten in the
cor re spond ing Port 1 register bit. To confi gure any of these pins
as digital inputs, the user should write a 0 to these port bits to
confi gure the cor re spond ing pin as a high im ped ance digital input.
Figure 39 il lus trates this function. Note that there are no output
drivers for Port 1 pins, and they there fore cannot be used as
outputs.
Port 2
Port 2 is a bidirectional port with internal pull-up resistors di rect ly
controlled via the P2 SFR. Port 2 also emits the high order address
bytes during fetches from external program mem o ry and middle
and high order address bytes during ac cess es to the 24-bit external
data memory space.
As shown in Figure 40, the output drivers of Port 2 are swit ch able
to an internal ADDR bus by an internal CON TROL signal for use
in external memory accesses (as for Port 0). In external memory
addressing mode (CONTROL = 1), the port pins fea ture push/
pull operation controlled by the in ter nal address bus (ADDR line).
However, unlike the P0 SFR during external memory accesses,
the P2 SFR remains un changed.
In general-purpose I/O port mode, Port 2 pins that have 1s writ ten
to them are pulled high by the internal pull-ups (Figure 38), and in
that state can be used as inputs. As inputs, Port 2 pins being pulled
externally low will source current be cause of the internal pull-up
resistors. Port 2 pins with 0s writ ten to them will drive a logic low
output voltage (V
Port 3
Port 3 is a bidirectional port with internal pull-ups directly con trolled
via the P3 SFR.
Port 3 pins that have 1s written to them are pulled high by the
internal pull-ups, and in that state can be used as inputs. As inputs,
Port 3 pins being pulled externally low will source cur rent because
of the internal pull-ups. Port 3 pins with 0s writ ten to them will
drive a logic low output voltage (V
ing 1.6 mA.
ADuC836
TO LATCH
INTERNAL
LATCH
WRITE
Figure 39. P1.2 to P1.7 Bit Latch and I/O Buffer
READ
READ
BUS
PIN
INTERNAL
TO LATCH
Figure 40. Port 2 Bit Latch and I/O Buffer
LATCH
WRITE
READ
READ
BUS
PIN
OL
) and will be capable of sinking 1.6 mA.
LATCH
CL
D
Q
TO ADC
LATCH
D
CL
ADDR
*SEE FIGURE 38 FOR
DETAILS OF INTERNAL PULL-UP
Q
CONTROL
OL
) and will be capable of sink-
DV
DD
DV
P1.x
PIN
DD
INTERNAL
PULL-UP*
P2.x
PIN
–50–
Port 3 pins also have various secondary functions described in
Table XXV. The alternate functions of Port 3 pins can be activated
only if the corresponding bit latch in the P3 SFR contains a 1.
Otherwise, the port pin is stuck at 0.
Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Port 3 pins have the same bit latch and I/O buffer con fi g u ra tions
as the P1.0 and P1.1, as shown in Figure 41. The internal pull-up
confi guration is also defi ned by the one in Figure 38.
Additional Digital I/O
In addition to the port pins, the dedicated SPI/I2C pins (SCLOCK
and SDATA/MOSI) also feature both input and output func tions.
Their equivalent I/O architectures are il lus trat ed in Figure 42 and
Figure 44, respectively, for SPI operation, and in Figure 43 and
Figure 45 for I
Notice that in I
disabled leaving only a weak pull-up (Q2) present. By con trast, in
SPI mode (SPE = 1), the strong pull-up FET (Q1) is controlled
directly by SPI hardware, giving the pin push/pull capability.
In I
op er ate in parallel in order to provide an extra 60% or 70% of
cur rent sinking capability. In SPI mode, however, (SPE = 1), only
one of the pull-down FETs (Q3) operates on each pin re sult ing
in sink capabilities identical to that of Port 0 and Port 2 pins.
On the input path of SCLOCK, notice that a Schmitt trigger
conditions the signal going to the SPI hardware to prevent false
triggers (double triggers) on slow incoming edges. For incoming
signals from the SCLOCK and SDATA pins going to I
a fi lter conditions the signals to reject glitches of up to 50 ns in
duration.
2
INTERNAL
TO LATCH
C mode (SPE = 0), two pull-down FETs (Q3 and Q4)
LATCH
WRITE
READ
READ
BUS
PIN
Table XXV. Port 3, Alternate Pin Functions
Figure 41. Port 3 Bit Latch and I/O Buffer
Alternate Function
RxD (UART Input Pin)
(or Serial Data I/O in Mode 0)
TxD (UART Output Pin)
(or Serial Clock Output in Mode 0)
T0 (Timer/Counter 0 External Input)
PWMCLK (PWM External Clock)
T1 (Timer/Counter 1 External Input)
2
2
C operation.
C mode (SPE = 0), the strong pull-up FET (Q1) is
(External Data Memory Read Strobe)
(External Data Memory Write Strobe)
(External Interrupt 0)
(External Interrupt 1)
LATCH
D
CL
Q
ALTERNATE
ALTERNATE
FUNCTION
FUNCTION
OUTPUT
INPUT
DV
DD
INTERNAL
PULL-UP*
*SEE FIGURE 38
FOR DETAILS OF
INTERNAL PULL-UP
P3.x
PIN
2
C hard ware,
REV. 0