EVAL-ADUC836QS AD [Analog Devices], EVAL-ADUC836QS Datasheet - Page 20

• Manufacturer Part Number: EVAL-ADUC836QS
• Description: MicroConverter, Dual 16-Bit ADCs with Embedded 62 kB Flash MCU
• Manufacturer: AD [Analog Devices]

ADC0H/ADC0M (Primary ADC Conversion Result Reg is ters)
These two 8-bit registers hold the 16-bit conversion result from the primary ADC.
SFR Address
Power-On Default Value
Bit Addressable
ADC1H/ADC1L (Auxiliary ADC Conversion Result Registers)
These two 8-bit registers hold the 16-bit conversion result from the auxiliary ADC.
SFR Address
Power-On Default Value
Bit Addressable
OF0H/OF0M (Primary ADC Offset Calibration Registers*)
These two 8-bit registers hold the 16-bit offset calibration coeffi cient for the primary ADC. These registers are confi gured at pow er-on
with a factory default value of 800000H. How ev er, these bytes will be au to mat i cal ly overwritten if an internal or sys tem zero-scale
calibration of the primary ADC is initiated by the user via MD2–0 bits in the ADCMODE Register.
SFR Address
Power-On Default Value
Bit Addressable
OF1H/OF1L (Auxiliary ADC Offset Calibration Registers*)
These two 8-bit registers hold the 16-bit offset calibration coeffi cient for the auxiliary ADC. These registers are con fi g ured at pow er-on
with a factory default value of 8000H. How ev er, these bytes will be au to mat i cal ly overwritten if an internal or system zero-scale cal i bra tion
of the auxiliary ADC is initiated by the user via the MD2–0 bits in the ADCMODE Register.
SFR Address
Power-On Default Value
Bit Addressable
GN0H/GN0M (Primary ADC Gain Calibration Registers*)
These two 8-bit registers hold the 16-bit gain cal i bra tion coeffi cient for the primary ADC. These registers are con fi g ured at pow er-on
with a factory-calculated internal full-scale calibration coeffi cient. Every device will have an individual coeffi cient. How ev er, these bytes
will be au to mat i cal ly overwritten if an internal or sys tem full-scale calibration of the primary ADC is initiated by the user via MD2–0
bits in the ADCMODE Register.
SFR Address
Power-On Default Value
Bit Addressable
GN1H/GN1L (Auxiliary ADC Gain Calibration Registers*)
These two 8-bit registers hold the 16-bit gain calibration coeffi cient for the auxiliary ADC. These registers are con fi g ured at power-on
with a factory-calculated internal full-scale cal i bra tion coeffi cient. Every device will have an individual coeffi cient. However, these bytes
will be au to mat i cal ly overwritten if an internal or system full-scale calibration of the auxiliary ADC is initiated by the user via MD2–0
bits in the ADCMODE Register.
SFR Address
Power-On Default Value
Bit Addressable
*These registers can be overwritten by user software only if Mode bits MD0–2 (ADCMODE SFR) are zero.
ADuC836
ADC0M
ADC1L
ADC0H
00H
No
ADC1H
00H
No
OF0H
OF0M
80000H
No
OF1H
OF1L
8000H
No
GN0H
GN0M
No
GN1H
GN1L
No
High Data Byte
Middle Data Byte
ADC0H, ADC0M
ADC0H, ADC0M
High Data Byte
Low Data Byte
ADC1H, ADC1L
ADC1H, ADC1L
Primary ADC Offset Coeffi cient High Byte
Primary ADC Offset Coeffi cient Middle Byte
OF0H, OF0M respectively
OF0H, OF0M
Auxiliary ADC Offset Coeffi cient High Byte
Aux il ia ry ADC Offset Co ef fi cient Low Byte
OF1H and OF1L, respectively
OF1H, OF1L
Primary ADC Gain Coeffi cient High Byte
Pri ma ry ADC Gain Coeffi cient Middle Byte
Con fi g ured at Factory Final Test; See Notes above.
GN0H, GN0M
Auxiliary ADC Gain Coeffi cient High Byte
Auxiliary ADC Gain Coeffi cient Low Byte
Con fi g ured at Factory Final Test; see notes above.
GN1H, GN1L
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DBH
DAH
DDH
DCH
E3H
E2H
E5H
E4H
EBH
EAH
EDH
ECH
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