EVAL-ADUC836QS AD [Analog Devices], EVAL-ADUC836QS Datasheet - Page 18

• Manufacturer Part Number: EVAL-ADUC836QS
• Description: MicroConverter, Dual 16-Bit ADCs with Embedded 62 kB Flash MCU
• Manufacturer: AD [Analog Devices]

ADCMODE (ADC Mode Register)
Used to control the operational mode of both ADCs.
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
NOTES
1. Any change to the MD bits will immediately reset both ADCs. A write to the MD2–0 bits with no change is also treated as a reset. (See exception to this in Note 3.)
2. If ADC0CON is written when ADC0EN = 1, or if ADC0EN is changed from 0 to 1, then both ADCs are also immediately reset. In other words, the primary ADC is
3. On the other hand, if ADC1CON is written or if ADC1EN is changed from 0 to 1, only the auxiliary ADC is reset. For example, if the primary ADC is con tin u ous ly converting
4. Once ADCMODE has been written with a calibration mode, the RDY0/1 bits (ADCSTAT) are im me di ate ly reset and the calibration commences. On com ple tion, the appropriate
5. Any calibration request of the auxiliary ADC while the temperature sensor is selected will fail to complete. Although the RDY1 bit will be set at the end of the calibration
6. Calibrations are performed at maximum SF (see SF SFR) value, guaranteeing optimum calibration operation.
ADuC836
given priority over the auxiliary ADC, and any change requested on the primary ADC is immediately responded to.
when the auxiliary ADC change or enable occurs, the primary ADC continues undisturbed. Rather than allow the auxiliary ADC to op er ate with a phase difference from
the primary ADC, the auxiliary ADC will fall into step with the outputs of the pri ma ry ADC. The result is that the fi rst con ver sion time for the auxiliary ADC will be
delayed up to three outputs while the auxiliary ADC update rate is syn chro nized to the pri ma ry ADC.
calibration registers are written, the relevant bits in ADCSTAT are written, and the MD2–0 bits are reset to 000 to indicate the ADC is back in Power-Down mode.
cycle, no update of the calibration SFRs will take place and the ERR1 bit will be set.
Name
–––
–––
ADC0EN
ADC1EN
–––
MD2
MD1
MD0
Description
Reserved for Future Use
Reserved for Future Use
Primary ADC Enable.
Set by the user to enable the primary ADC and place it in the mode selected in MD2–MD0, below.
Cleared by the user to place the primary ADC in power-down mode.
Auxiliary ADC Enable.
Set by the user to enable the auxiliary ADC and place it in the mode selected in MD2–MD0, below.
Cleared by the user to place the auxiliary ADC in power-down mode.
Reserved for Future Use
Primary and Auxiliary ADC Mode bits.
These bits select the operational mode of the enabled ADC as follows:
MD2
0
0
0
0
1
1
1
1
MD1
0
0
1
1
0
0
1
1
D1H
00H
No
MD0
0
1
0
1
0
1
0
1
Table V. ADCMODE SFR Bit Designations
ADC input(s).
ADC0/1CON Register.
ADC0/1CON Register.
ADC Power-Down Mode (Power-On Default)
Idle Mode. The ADC fi lter and modulator are held in a reset state although the
modulator clocks are still pro vid ed.
Single Conversion Mode. A single con ver sion is performed on the enabled ADC.
On completion of the conversion, the ADC data registers (ADC0H/M and/or ADC1H/L)
are up dat ed, the relevant fl ags in the ADCSTAT SFR are writ ten, and power-down is
re-entered with the MD2–MD0 ac cord ing ly being written to 000.
Con tin u ous Conversion. The ADC data registers are reg u lar ly updated at the selected
update rate (see SF Register).
Internal Zero-Scale Calibration. Internal short automatically connected to the enabled
In ter nal Full-Scale Calibration. Internal or external V
and XREF1 bits in ADC0/1CON) is automatically connected to the enabled ADC
input(s) for this cal i bra tion.
System Zero-Scale Calibration. User should connect system zero-scale input to the
enabled ADC input(s) as selected by CH1/CH0 and ACH1/ACH0 bits in the
System Full-Scale Calibration. User should connect system full-scale input to the
enabled ADC input(s) as selected by the CH1/CH0 and ACH1/ACH0 bits in the
–18–
REF
(as determined by XREF0
REV. 0