AM29SL400DB90 SPANSION [SPANSION], AM29SL400DB90 Datasheet - Page 10

• Manufacturer Part Number: AM29SL400DB90
• Description: 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory
• Manufacturer: SPANSION [SPANSION]

DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
Legend:
L = Logic Low = V
Notes:
1. Addresses are A17:A0 in word mode (BYTE# = V
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configura-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and con-
trolled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
8
Read
Write
Standby
Output Disable
Reset
Sector Protect (Note 2)
Sector Unprotect (Note 2)
Temporary Sector Unprotect
Protection/Unprotection” section.
Operation
IL
, H = Logic High = V
V
0.2 V
CE#
CC
Table 1. Am29SL400D Device Bus Operations
X
X
A D V A N C E
L
L
L
L
L
IL
±
. CE# is the power
IH
OE# WE# RESET#
, V
H
X
H
X
H
H
X
L
ID
= 10 ± 1.0 V, X = Don’t Care, A
H
X
H
X
X
L
L
L
IH
), A17:A-1 in byte mode (BYTE# = V
V
0.2 V
Am29SL400D
V
V
V
CC
H
H
H
L
ID
ID
ID
I N F O R M A T I O N
±
Sector Address,
Sector Address,
A6 = H, A1 = H,
A6 = L, A1 = H,
the register serve as inputs to the internal state
machine. The state machine outputs dictate the func-
tion of the device.
tions, the inputs and control levels they require, and the
resulting output. The following subsections describe
each of these operations in further detail.
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
should remain at V
whether the device outputs array data in words or
bytes.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
Addresses
(Note 1)
A0 = L
A0 = L
A
A
A
X
X
X
IN
IN
IN
IN
= Address In, D
High-Z
High-Z
High-Z
DQ0–
D
DQ7
D
D
D
D
Table 1
OUT
IN
IN
IN
IN
IH
IL
. The BYTE# pin determines
).
BYTE#
High-Z
High-Z
High-Z
= V
D
IN
Rev. A Amend. +1 April 13, 2005
D
D
lists the device bus opera-
OUT
X
X
= Data In, D
IN
IN
IH
DQ8–DQ14 = High-Z,
DQ8–DQ15
DQ15 = A-1
OUT
BYTE#
High-Z
High-Z
High-Z
High-Z
= V
X
X
= Data Out
IL