AM29SL400DB90 SPANSION [SPANSION], AM29SL400DB90 Datasheet - Page 11

• Manufacturer Part Number: AM29SL400DB90
• Description: 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory
• Manufacturer: SPANSION [SPANSION]

See “ Reading Array Data, on page 13 for more infor-
mation. Refer to the AC Read Operations table for
timing specifications and to
the timing diagram. I
represents the active current specification for reading
array data.
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to Word/Byte Configuration, on page 8
for more information.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are
required to program a word or byte, instead of four. The
has details on programming data to the device using
b o t h s t a n d a r d a n d U n l o ck B y p a s s c o m m a n d
sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector
address” consists of the address bits required to
u n i q u e l y s e l e c t a s e c t o r. T h e
Definitions, on page 17 has details on erasing a sector
or the entire chip, or suspending/resuming the erase
operation.
After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
in this mode. Refer to the Autoselect Mode and Autose-
lect Command Sequence sections for more informa-
tion.
I
active current specification for the write mode. The AC
Characteristics, on page 26 contains timing specifica-
tion tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
read specifications apply. Refer to Write Operation
Status, on page 18 for more information, and to AC
Characteristics, on page 26 for timing diagrams.
April 13, 2005 Rev. A Amend. +1
Word/Byte Program Command Sequence, on page 14
CC2
in the DC Characteristics table represents the
IL
, and OE# to V
CC1
in the DC Characteristics table
IH
.
Figure 13, on page 26
A D V A N C E
C o m m a n d
Am29SL400D
for
CC
I N F O R M A T I O N
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V
(Note that this is a more restricted voltage range than
V
V
the standby current will be greater. The device requires
standard access time (t
device is in either of these standby modes, before it is
ready to read data.
The device also enters the standby mode when the
RESET# pin is driven low. Refer to the next section,
RESET#: Hardware Reset Pin.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain stable for t
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. I
Characteristics table represents the automatic sleep
mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the
RESET# pin is driven low for at least a period of t
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state
machine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to
ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
at V
be greater.
CC3
IH
CC
.) If CE# and RESET# are held at V
IL
± 0.2 V, the device will be in the standby mode, but
in the DC Characteristics table represents the
but not within V
SS
±0.2 V, the standby current will
CE
) for read access when the
CC4
SS
). If RESET# is held
±0.2 V, the device
IH
CC4
, but not within
CC
in the DC
ACC
± 0.2 V.
RP
+ 50
, the
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