AM29SL400DB90 SPANSION [SPANSION], AM29SL400DB90 Datasheet - Page 15

• Manufacturer Part Number: AM29SL400DB90
• Description: 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory
• Manufacturer: SPANSION [SPANSION]

Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations.
ister command sequences. Writing incorrect address
and data values or writing them in the improper
sequence resets the device to reading array data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in AC
Characteristics, on page 26 .
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The
system can read array data using the standard read
timings, except that if it reads at an address within
April 13, 2005 Rev. A Amend. +1
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
Figure 2. Temporary Sector Unprotect Operation
again.
Table 5 on page 17
Unprotect Completed
Program Operations
Temporary Sector
Perform Erase or
RESET# = V
RESET# = V
(Note 2)
START
A D V A N C E
defines the valid reg-
Table 5 on page 17
ID
IH
Am29SL400D
I N F O R M A T I O N
for command definitions). In addition, the following
hardware data protection measures prevent accidental
erasure or programming, which might otherwise be
caused by spurious system level signals during V
power-up and power-down transitions, or from system
noise.
Low V
When V
accept any write cycles. This protects data during V
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V
proper signals to the control pins to prevent uninten-
tional writes when V
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more infor-
mation on this mode.
The system must issue the reset command to
re-enable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the Reset
Command section, next.
See also
page 8
table provides the read parameters, and
page 26
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command.
The reset command may be written between the
sequence cycles in an erase command sequence
IL
, CE# = V
CC
for more information. The Read Operations
CC
shows the timing diagram.
Write Inhibit
Requirements for Reading Array Data, on
is less than V
IH
or WE# = V
IL
LKO
and OE# = V
CC
. The system must provide the
is greater than V
LKO
IH
. To initiate a write cycle,
, the device does not
IH
during power up, the
LKO
Figure 13, on
.
CC
CC
CC
13