CYIL1SM0300AA CYPRESS [Cypress Semiconductor], CYIL1SM0300AA Datasheet - Page 11

• Manufacturer Part Number: CYIL1SM0300AA
• Description: LUPA-300 CMOS Image Sensor
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document Number: 001-00371 Rev. *D
by the register FT_TIMER. Section 3.1 explains the use of this
register.
Table 7. Typical frame rates for 80-MHz clock and
GRAN<1:0>=10
Programmable Gain Amplifiers
The programmable gain amplifiers have two functions:
Adding an offset to the signal to fit it into the range of the ADC.
This is controlled by the VBLACK and VOFFSET SPI settings.
Amplifying the signal after the offset has been added.
Offset Regulation
The purpose of the offset regulation is to bring the signal in the
input range of the ADC.
After the column amplifiers the signal from the pixels has a
range from 0.1V (bright) to 1.3V (black). The input range of the
ADC is from 0.75V to 1.75V. The amount of offset added is
controlled
VOFFSET<7:0>. The formula for adding offset is:
resolution
640 x 480
640 x 240
256 x 256
ADC_OUT
Image
(X * Y)
CLK_ADC
ADC_IN
<9:0>
by
Frame rate
two
247.5
488.3
1076
(fps)
SPI
D1
settings:
Data rate
Input range
Quantization
DNL
INL
readout (us)
50ns
Frame
4038
2048
929
D2
VBLACK<7:0>
Parameter
5.5 clock cycles
sub sampling
DUMMY
Comment
windowing
D3
Table 8. ADC Parameters
Figure 5. ADC Timing
and
D4
20 Msamples/s
0.75V - 1.75 V
10 bit
Typ. < 0.3 LSB
Typ. < 0.7 LSB
Analog to Digital Converter
The sensor has four 10-bit pipelined ADC on board. The ADCs
are nominally operating at 20 Msamples/s. The input range of
the ADC is between 0.75 and 1.75V. The analog input signal
is sampled at 2.1 ns delay from the rising edge of the ADC
clock.
The digital output data appears at the output at 5.5 cycles later.
This is at the 6th falling edge succeeding the sample moment.
The data is delayed by 3.7 ns with respect to this falling edge.
This is illustrated in Figure 5.
Voutput = Vsignal + (Voffset - Vblack)
One should know that the FPN (fixed pattern noise) of the
sensor causes a spread of about 100 mV on the dark level. To
allow FPN correction during post processing of the image, this
spread on the dark level needs to be covered by the input
range of the ADC. This is the reason why the default settings
of the SPI are programmed to add an offset of 200 mV. This
way the dark level goes from 1.3V to 1.5V and is the FPN
information still converted by the ADC. To even better match
the ADC range we advice to program a offset of 340 mV. To
program this offset the Voffset and Vblack registers can be
used. See section 3.8 for more explanation. Figure 6 illus-
trates the operation of the offset regulation with an example.
The blue histogram is the histogram of the image taken after
the column amplifiers. Let's say the device has a black level of
D5
Specification
3.7ns
D6
D1
D7
D2
CYIL1SM0300AA
D8
D3
Page 11 of 36
D4
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