CYIL1SM0300AA CYPRESS [Cypress Semiconductor], CYIL1SM0300AA Datasheet - Page 9

• Manufacturer Part Number: CYIL1SM0300AA
• Description: LUPA-300 CMOS Image Sensor
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document Number: 001-00371 Rev. *D
Sensor Architecture
The floor plan of the architecture is shown in the block diagram
below. The image core consists of a pixel array, an X- and
Y-addressing register, pixel array drivers and column
amplifiers. The image sensor of 640 x 480 pixels is read out in
progressive scan.
The architecture allows programmable addressing in the
x-direction in steps of 8 pixels and in the y-direction in steps of
The 6-T pixel
To obtain the global shutter feature combined with a high
sensitivity and good Parasitic Light Sensitivity (PLS), the pixel
architecture given in the figure below is implemented. This
PGA + ADC
Figure 3. Floor Plan of the Sensor
PGA + ADC
Column amplifiers
On chip drivers
X-shift register
10 bit output
Pixel array
640 x 480
Mux
1 pixel. The starting point of the address is uploadable by
means of the Serial Parallel Interface (SPI).
The PGAs amplify the signal from the column and add an
offset so the signal fits in the input range of the ADC. The four
ADCs then convert the signal to the digital domain. Pixels are
selected in a 4 * 1 kernel. Every ADC samples the signal from
one of the 4 selected pixels. Sampling frequency is 20 MHz.
The digital outputs of the 4 ADCs are multiplexed to one output
bus operating at 80 MHz.
pixel architecture is designed in a 9.9 x 9.9 m2 pixel pitch. The
pixel is designed to meet the specifications as described in
Table 1, Table 2 and Table 3.
PGA + ADC
Sequencer
PGA + ADC
CYIL1SM0300AA
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