CYIL1SM0300AA CYPRESS [Cypress Semiconductor], CYIL1SM0300AA Datasheet - Page 27

• Manufacturer Part Number: CYIL1SM0300AA
• Description: LUPA-300 CMOS Image Sensor
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document Number: 001-00371 Rev. *D
Startup Timing
On start-up VDDD should rise together with or before the other
supplies. The rise of VDDD should be limited to 1V/100 µs to
avoid the activation of the on chip ESD protection circuitry.
During the rise of VDDD an on chip POR_N signal is
generated that resets the SPI registers to its default setting.
After VDDD is stable the SPI settings can be uploaded to
configure the sensor for future readout and light integration.
When powering on the VDDD supply, the RESET_N pin
Sequencer Reset Timing
By bringing RESET_N low for at least 50 ns, the on chip
sequencer is reset to its initial state. The internal clock division
is restarted. The second rising edge of CLK after the rising
3. After the desired integration length all INT_TIME_x should
System clock
VDDD power
RESET_N
Core clock
SPI upload
(external)
(internal)
POR_N
(internal)
Core clock
RESET_N
(external)
simultaneous go low to start the FOT.
(internal)
(internal)
supply
System
(internal)
Sync_Y
Clock_Y
clock
INT_TIME1
POWER ON
INVALID
Normal operation
FOT
Min 500ns
SPI upload
Figure 23. Sequencer Reset Timing
Reset
Figure 22. Start-Up Timing
Readout
Min 50 ns
INVALID
should be kept low to reset the on chip sequencer and
addressing logic. The RESET_N pin must remain low until all
initial SPI settings are uploaded. RESET_N pin must remain
low for at least 500 ns after ALL supplies are stable. The rising
edge of RESET_N starts the on chip clock division. The
second rising edge of CLK after the rising edge of RESET_N,
triggers the rising edge of the core clock. Some SPI settings
can be uploaded after the core clock has started. See the
chapter about the SPI settings for this.
edge of RESET_N the internal clock is restarted. The SPI
settings are not affected by RESET_N. If needed the SPI
settings can be changed during a low level of RESET_N.
VDDD STABLE
INVALID
Integration
LINE_VALIDs
Dummy
SPI upload if required
CYIL1SM0300AA
FOT
Normal operation
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