CYIL1SM0300AA CYPRESS [Cypress Semiconductor], CYIL1SM0300AA Datasheet - Page 21

• Manufacturer Part Number: CYIL1SM0300AA
• Description: LUPA-300 CMOS Image Sensor
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document Number: 001-00371 Rev. *D
Timing and Readout of the Image Sensor
The timing of the sensor consists of 2 parts. The first part is
related with the integration time and the control of the pixel.
The second part is related with the readout of the image
sensor. Integration and readout can be in parallel. In this case
the integration time of frame I is ongoing during readout of
frame I-1. Figure 13 shows this parallel timing structure.
The readout of every frame starts with a Frame Overhead
Time (FOT) during which the analog value on the pixel diode
is transferred to the pixel memory element. After this FOT, the
sensor is read out line per line. The readout of every line starts
with a Row Overhead Time (ROT) during which the pixel value
Integration Timing
Integration Timing in Mastermode
In mastermode the integration time, the dual slope (DS)
integration time and triple slope (TS) integration time are set
by the SPI settings. Figure 14 shows the integration timing and
the relationship with the SPI registers. The timing concerning
integration is expressed in number of lines read out. The
timing is controlled by 4 SPI registers which need to be
uploaded with the desired number of lines. This number is then
compared with the line counter that keeps track of the number
of lines that is read out.
RES1_LENGTH <11:0>: The number of lines read out (minus
1) after which the pixel reset will drop and the integration will
start.
FOT
ROT
Integration frame I+1
Readout frame I
L1
K1
L2
K2
Figure 13. Global Readout Timing
Readout Pixels
Readout Lines
...
...
is put on the column lines. Then the pixels are selected in
groups of 4. So in total 160 kernels of 4 pixels are read out.
The internal timing is generated by the sequencer. The
sequencer can operate in 2 modes: master mode and slave
mode. In master mode all the internal timing is controlled by
the sequencer, based on the SPI settings. In slave mode the
integration timing is directly controlled over three pins, the
readout timing is still controlled by the sequencer. The
selection between master and slave mode is done by the
MASTERMODE register of the SPI. The sequencer is clocked
on the core clock; this is the same clock as the ADCs. The core
clock is the input clock divided by 4.
RES2_TIMER <11:0>: The number of lines read out (minus 1)
after which the dual slope reset pulse will be given. The length
of the pulse is given by the formula: 4*(12*(GRAN<1:0>+1)+1)
(in clock cycles).
RES3_TIMER < 11:0>: The number of lines read out (minus
1) after which the triple slope reset pulse will be given. The
length
4*(12*(GRAN<1:0>+1)+1) (in clock cycles).
FT_TIMER <11:0>: The number of lines read out (minus 1)
after which the Frame Transfer (FT) and the FOT will start. The
length
4*(12*(GRAN<1:0>+1)+1) (in clock cycles).
Integration frame I + 2
of
of
Readout frame I+1
L480
K160
the
the
pulse
pulse
is
is
CYIL1SM0300AA
given
given
by
by
Page 21 of 36
the
the
formula:
formula:
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