MT90823AL1 ZARLINK [Zarlink Semiconductor Inc], MT90823AL1 Datasheet - Page 14

• Manufacturer Part Number: MT90823AL1
• Description: 3V Large Digital Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

MT90823
Data Sheet
The data in the control register consists of the memory block programming bit (MBP), the memory select bit (MS)
and the stream address bits (STA). The memory block programming bit allows users to program the entire
connection memory block, (see “Memory Block Programming” ). The memory select bit controls the selection of the
connection memory or the data Memory. The stream address bits define an internal memory subsections
corresponding to input or output ST-BUS streams.
The data in the IMS register consists of block programming bits (BPD0-BPD4), block programming enable bit
(BPE), output standby bit (OSB), start frame evaluation bit (SFE) and data rate selection bits (DR0, DR1). The block
programming and the block programming enable bits allows users to program the entire connection memory, (see
Memory Block Programming section). If the ODE pin is low, the OSB bit enables (if high) or disables (if low) all ST-
BUS output drivers. If the ODE pin is high, the contents of the OSB bit is ignored and all ST-BUS output drivers are
enabled.
Connection Memory Control
The contents of the CSTo bit of each connection memory location are output on the CSTo pin once every frame.
The CSTo pin is a 4.096, 8.192 or 16.384 Mb/s output carrying 512, 1,024 or 2,048 bits respectively. If the CSTo bit
is set high, the corresponding bit on the CSTo output is transmitted high. If the CSTo bit is low, the corresponding bit
on the CSTo output is transmitted low. The contents of the CSTo bits of the connection memory are transmitted
sequentially via the CSTo pin and are synchronous with the data rates on the other ST-BUS streams.
The CSTo bit is output one channel before the corresponding channel on the ST-BUS. For example, in 2 Mb/s
mode, the contents of the CSTo bit in position 0 (STo0, CH0) of the connection memory is output on the first clock
cycle of channel 31 via CSTo pin. The contents of the CSTo bit in position 32 (STo1, CH0) of the connection
memory is output on the second clock cycle of channel 31 via CSTo pin.
When either the ODE pin or the OSB bit is high, the OE bit of each connection memory location enables (if high) or
disables (if low) the output drivers for an individual ST-BUS output stream and channel. Table 5 details this function.
The connection memory message channel (MC) bit (if high) enables message mode in the associated ST-BUS
output channel. When message mode is enabled, only the lower half (8 least significant bits) of the connection
memory is transferred to the ST-BUS outputs.
If the MC bit is low, the contents of the connection memory stream address bit (SAB) and channel address bit
(CAB) defines the source information (stream and channel) of the time-slot that will be switched to the output.
Bit V/C (Variable/Constant Delay) of each connection memory location allows the per-channel selection between
variable and constant throughput delay modes.
The loopback bit should be used for diagnostic purpose only; this bit should be set to zero for normal operation. If
all LPBK bits are set high for all connection memory locations, the associated ST-BUS output channel data is
internally looped back to the ST-BUS input channel (i.e., SToN channel m data loops back to STi N channel m).
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