MT90823AL1 ZARLINK [Zarlink Semiconductor Inc], MT90823AL1 Datasheet - Page 5

• Manufacturer Part Number: MT90823AL1
• Description: 3V Large Digital Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin Description
30, 54
64, 75
PLCC
2, 32,
3 - 10
1, 11,
12 -
84
63
27
28
29
31
33
34
31, 41,
56, 66,
MQFP
76, 99
5, 40,
68-75
81-96
100
100
67
97
98
6
7
LQFP
64,98
100
65 -
78 -
28,
38,
53,
63,
73,
37,
Pin #
96
72
93
94
95
97
3
4
C1,C2,D1,D2,E1,
E2,F1,F2,G1,G2,
L3,L5,L7,L9,L11,
M1,M2,M12,M13
B6,A6,A5,B5,A4,
H1,H2,J1,J2,K1,
A1,A2,A12,A13,
H3,H11,K3,K11,
D3,D11,F3,F11,
C9,C11,E3,E11
C4,C6,C8,C10,
B13,C3,C5,C7,
B1,B2,B7,B12,
G3,G11,J3,J11,
L4,L6,L8,L10
B4,A3,B3
BGA
120
M3
K2
N1
N2
L1
L2
Zarlink Semiconductor Inc.
STo8 - 15 ST-BUS Output 8 to 15 (5 V Tolerant Three-state
FE/HCLK Frame Evaluation / HCLK Clock (5 V Tolerant
STi0 - 15 ST-BUS Input 0 to 15 (5 V Tolerant Inputs): Serial
Name
TMS
CLK
V
V
TDI
F0i
MT90823
DD
SS
5
Ground.
+3.3 Volt Power Supply.
Outputs): Serial data Output stream. These streams
may have data rates of 2.048, 4.096 or 8.192 Mb/s,
depending upon the value programmed at bits DR0 - 1
in the IMS register.
data input stream. These streams may have data rates
of 2.048, 4.096 or 8.192 Mb/s, depending upon the
value programmed at bits DR0 - 1 in the IMS register.
Frame Pulse (5 V Tolerant Input): When the WFPS
pin is low, this input accepts and automatically
identifies frame synchronization signals formatted
according to ST-BUS and GCI specifications. When the
WFPS pin is high, this pin accepts a negative frame
pulse which conforms to WFPS formats.
Input): When the WFPS pin is low, this pin is the frame
measurement input. When the WFPS pin is high, the
HCLK (4.096MHz clock) is required for frame
alignment in the wide frame pulse (WFP) mode.
Clock (5 V Tolerant Input): Serial clock for shifting
data in/out on the serial streams (STi/o 0 - 15).
Depending upon the value programmed at bits DR0 - 1
in the IMS register, this input accepts a 4.096, 8.192 or
16.384 MHz clock.
Test Mode Select (3.3 V Input with internal pull-up):
JTAG signal that controls the TAP controller state
transitions.
Test Serial Data In (3.3 V Tolerant Input with internal
pull-up): JTAG serial test instructions and data are
shifted in on this pin.
Description
Data Sheet