MT90823AL1 ZARLINK [Zarlink Semiconductor Inc], MT90823AL1 Datasheet - Page 7

• Manufacturer Part Number: MT90823AL1
• Description: 3V Large Digital Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin Description (continued)
PLCC
55 -
65 -
84
50
51
52
53
62
72
73
74
MQFP
32-39
42-49
100
23
24
25
26
50
55
LQFP
100
29 -
39 -
Pin #
20
21
22
23
36
46
47
48
G12,G13,F12,
F13,E12,E13,
L12,L13,K12,
K13,J12,J13,
H12,H13
D12,D13
BGA
M10
N12
M11
N13
C12
C13
120
R/W / WR Read/Write / Write (5 V Tolerant Input): In the cases
Zarlink Semiconductor Inc.
AS/ALE
AD0 - 7
D8 - 15
Name
CSTo
DTA
CS
IM
MT90823
7
of Motorola non-multiplexed and multiplexed bus
operations, this input is R/W. This input controls the
direction of the data bus lines (AD0 - AD7, D8-D15)
during a microprocessor access.
For multiplexed bus operation, this input is WR. This
active low input is used with RD to control the data bus
(AD0 - 7) lines as inputs.
Chip Select (5 V Tolerant Input): Active low input
used by a microprocessor to activate the
microprocessor port of MT90823.
Address Strobe or Latch Enable (5 V Tolerant
Input): This input is used if multiplexed bus operation
is selected via the IM input pin. For Motorola non-
multiplexed bus operation, connect this pin to ground.
CPU Interface Mode (5 V Tolerant Input): When IM is
high, the microprocessor port is in the multiplexed
mode. When IM is low, the microprocessor port is in
non-multiplexed mode.
Address/Data Bus 0 to 7 (5 V Tolerant I/O): These
pins are the eight least significant data bits of the
microprocessor port. In multiplexed mode, these pins
are also the input address bits of the microprocessor
port.
Data Bus 8-15 (5 V Tolerant I/O): These pins are the
eight most significant data bits of the microprocessor
port.
Data Transfer Acknowledgement (5 V tolerant
Three-state Output): Indicates that a data bus transfer
is complete. When the bus cycle ends, this pin drives
HIGH and then tri-states, allowing for faster bus cycles
with a weaker pull-up resistor. A pull-up resistor is
required to hold a HIGH level when the pin is tri-stated.
Control Output (5 V Tolerant Output). This is a
4.096, 8.192 or 16.384 Mb/s output containing 512,
1024 or 2048 bits per frame respectively. The level of
each bit is determined by the CSTo bit in the
connection memory. See External Drive Control
Section.
Description
Data Sheet